Wafer level packaging method

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

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Details

C438S114000, C438S118000, C438S401000, C438S462000, C438S465000, C438S464000, C257SE21503, C257SE21599, C257SE23179, C257SE21499

Reexamination Certificate

active

07972904

ABSTRACT:
A wafer level packaging method is revealed. Firstly, a wafer with a plurality of bumps disposed on a surface is provided. Placing a dielectric tape on a mold plate is followed. Then, the wafer is laminated with the mold plate to make the dielectric tape be compliantly bonded to the surface of the wafer and to make the bumps be embedded in the dielectric tape. After removing the mold plate, flattening the dielectric tape to form a plurality of exposed surfaces of the bumps wherein the exposed surfaces and the flattened surface of the dielectric tape are coplanar. Therefore, the exposed surfaces of the bumps can be regarded as effective alignment points for easy pattern recognition of the wafer level packaged wafers during singulation process.

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patent: 6399178 (2002-06-01), Chung
patent: 6455353 (2002-09-01), Lin
patent: 6500764 (2002-12-01), Pritchett
patent: 6818550 (2004-11-01), Shibata
patent: 7776649 (2010-08-01), Fan
patent: 2001/0055834 (2001-12-01), Lin
patent: 2005/0048693 (2005-03-01), Yoon
patent: 2008/0265445 (2008-10-01), Feger et al.
patent: 2009/0079052 (2009-03-01), Youn
patent: 2009/0200675 (2009-08-01), Goebel et al.

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