Wafer level packaging for making flip-chips

Details Wafer level packaging for making flip-chips Wafer level packaging for making flip-chips

2001-11-28

2003-08-12

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

With measuring or testing

C438S012000, C438S004000

Reexamination Certificate

active

06605480

ABSTRACT:

FIELD OF THE INVENTION
The present invention is relating to integrated circuit (IC) manufacture technology, more particularly to a wafer level packaging process for making flip-chips with temporarily protected fuses and integrated circuits formed by the process.
BACKGROUND OF THE INVENTION
It is common that complicated integrated circuits have fuse structures, especially for high-capacity memory chips and single chips with system function. The fuse structures are connecting integrated circuits and redundant circuits. If defective circuits of integrated circuit are found after testing, then the corresponding fuse structures are struck by laser beam to replace defective circuits with redundant circuits, that is so-called “laser repair”.
A testing process of semiconductor devices is described from U.S. Pat. No. 5,326,709 entitled “Wafer testing process of a semiconductor device comprising a redundancy circuit”. The semiconductor device has a redundant circuit. At first PSG and nitride films are partially etched on a wafer for opening bonding pads. Thereafter, “testing before laser repairing”, “laser repairing”, “testing the repaired chips”, and “off-line inking” are executed in order. Therefore, it is general that “laser repair” is executed in bare chip configuration, then, dicing and packaging of respective chips are executed. The wafer level packaging process doesn't include “bumping” step for making flip-chips. Besides, the passivation layer above the fuse usually is thinner such as dimples or fuse windows (referring to U.S. Pat. No. 6,121,073). It is beneficial for laser beam to strike but easy to cause pollution and oxygenation problems on fuses in the manufacturing process of bumping and wafer level burn-in.
An integrated circuit with fuse structure is described from U.S. Pat. No. 5,729,041 “Protective film for fuse window passivation for semiconductor integrated circuit applications”. As shown in
FIG. 10
, an integrated circuit
10
has a silicon substrate
11
on which a field oxide
12
of insulating silicon dioxide (SiO2) is formed to support the fuse
13
of tungsten or polycide. A plurality of insulating layers such as silicon oxide layer
14
, spin on glass
15
, and silicon oxide layer
16
are further formed on silicon substrate
11
and field oxide
12
. The insulating layers
14
,
15
,
16
forms an opening
17
corresponding to fuse
13
, so that there is no insulating layer above fuse
13
. Also a permanent protective layer
18
is permanently formed on the exposing surface of silicon dioxide layer
16
and opening
17
. The protective layer
18
is laser-pervious over 50%, and properly protects the fuse
13
without detrimental influence on laser repair for preventing pollution or metal oxygenation. However, the high laser-pervious protection layer
18
will be on the integrated circuit
10
permanently after finishing manufacturing process, so that thickness, material, and manufacturing conditions of protective layer
18
must be precisely controlled. The protective layer
18
made from silane and ammonia is formed by means of plasma enhance chemical vapor deposition (PECVD) technique. The protective layer
18
is made of silicon and nitrogen which should be in the ratio of between 1 to 1.2 and 1 to 1.6, and its thickness must be between 3,000 and 15,000 angstrom. Besides, it is not described that the fuse structure with transparent protective layer
18
is how to be used in wafer level packaging process for making flip-chips.
SUMMARY
The main object of the present invention is to provide a wafer level packaging process for making flip-chips in order to solve the problem mentioned above. A material easy to remove such as photoresist or protective metal layer is formed in the depression portion above the fuse prior to bumping for ensuring the fuse structure will not to be polluted and oxygenated in the process of plating and bumping. The protective material is removed prior to laser repairing for protecting the fuse temporarily.
The another object of the present invention is to provide an integrated circuit having a protective material easy to be removed in the depression portions of insulating layer above fuses for temporary protection of the fuses.
According to the wafer level packaging process for making flip-chips of the present invention, a wafer includes a plurality of chips integrally, wherein each chip has a plurality of bonding pads, a plurality of fuses, and at least an insulating layer. The insulating layer exposes the bonding pads and has depression portions corresponding to the fuses. A protective material such as photoresist or protective metal layer is formed in the depression portions. A plurality of conductive bumps are formed on the bonding pads by evaporation, printing, sputtering or/and plating. Then, the protective material is removed. The wafer is probed for analyzing if there are fail chips required to be repaired. Laser beam strikes the fuses without the protective material in the corresponding depression portions for repairing chips, then the wafer is diced to singulate the flip chip.


REFERENCES:
patent: 5506499 (1996-04-01), Puar
patent: 5729041 (1998-03-01), Yoo et al.
patent: 6054340 (2000-04-01), Mitchell et al.
patent: 6121073 (2000-09-01), Huang et al.
patent: 405211219 (1993-08-01), None
patent: 10107063 (1998-04-01), None
IBM Tech. Discl. Bull. vol. 34, No. 8, (Jan. 1992), pp. 401-404. (Abstract pp. 1-3).

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