Wafer level packaging

Details Wafer level packaging Wafer level packaging

1997-11-04

2002-06-18

Louis-Jacques, Jacques H. (Department: 3661)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C174S050510, C174S050510, C257S673000, C257S691000, C257S693000, C257S735000, C257S666000, C029S825000, C029S827000, C029S830000, C029S841000, C029S846000

Reexamination Certificate

active

06407333

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit packaging, and more particularly to wafer level packaging of integrated circuits.
BACKGROUND OF THE INVENTION
The processes involved in the fabrication and packaging of circuit chips are well known. Typically, an array of identical circuits is patterned onto a circular semiconductor wafer using well known microlithographic techniques. The wafer is then sawed into many rectangular pieces to separate the individual circuits from one another, so that each circuit occupies its own circuit chip.
The chips are individually mounted onto lead frames, where they are held in place by means of an epoxy. A wire bonder is then used to establish electrical connections between the die pads on the chip and the respective leads of the lead frame.
With the chip physically and electrically attached to the lead frame, the chip and lead frame are placed into a mold equipment, where plastic is transfer molded to surround the assembly. This plastic packaging serves to protect the chip exposure to light, moisture and contamination, which could damage the circuit components, as well as making the entire assembly mechanically rigid and durable. The molded plastic is then cured by means of heating in an oven for several hours.
The leads of the lead frame are then trimmed and formed into the desired shape. For example, the leads may be formed into a “gull wing” shape for surface-mounted chips. At this stage, various electrical and mechanical tests are performed to determine whether the chip will function for its intended purpose.
The circuit chip industry is very cost-competitive. It is therefore desirable to shorten, streamline or eliminate packaging steps to shorten production time and reduce production costs for the chips.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for an improved integrated circuit packaging. The present invention provides a method of packaging integrated circuits at the wafer level. Additionally, the present invention provides a chip size package.
In accordance with the present invention, an integrated circuit package may include an integrated circuit chip. A lead frame may be opposite the circuit side of the integrated circuit chip. The lead frame may include at least one lead electrically coupled to the integrated circuit by a connector. The lead may be within a periphery of the integrated circuit chip. An encapsulant may cover the integrated circuit, the connector and a portion of the lead frame. A remaining portion of the lead frame may be exposed from the encapsulant.
More specifically, in accordance with one embodiment of the present invention, an integrated circuit may be packaged at the wafer level. In this embodiment, a strip of lead frames may be opposite a plurality of integrated circuit chips. The encapsulant may cover the integrated circuits and a portion of each lead frame. Each encapsulated integrated circuit and opposing lead frame may form a discrete integrated circuit package.
Important technical advantages of the present invention include providing chip size packages for integrated circuits. In particular, a lead frame, connectors and encapsulant do not extend beyond a periphery of an opposing integrated circuit chip. Accordingly, package volume is minimized and the chip may be used in devices requiring extremely small chips.
Another technical advantage of the present invention includes providing a method of packaging integrated circuit chips at the wafer level. In particular, integrated circuit chips may be packaged concurrently while still part of a wafer. Accordingly, the packaging process may be carried out as a continuation of the wafer fabrication process. This serves to streamline and shorten the assembly and packaging process.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.


REFERENCES:
patent: 4695870 (1987-09-01), Patraw
patent: 5384155 (1995-01-01), Abbott et al.
patent: 5519251 (1996-05-01), Sato et al.
patent: 5763829 (1998-06-01), Tomita et al.
patent: 5801439 (1998-09-01), Fujisawa et al.
patent: 5827999 (1998-10-01), McMillan et al.
patent: 5834691 (1998-11-01), Aoki
Drawing by Fujitsu of Chip Size Package, dated Feb. 1995.

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