Wafer level packages and methods of fabrication

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C438S106000, C257S691000, C257S690000

Reexamination Certificate

active

10938239

ABSTRACT:
A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

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Fujitsu Microelectronics America, Inc., “Super CSP,” pp. 17-19.
Elenius, Peter and Yang, Hong, “The Ultra CSP Wafer Scale Package,” High Density Interconnect Conference And Expo, Tempe, Arizona, Sep. 15-16, 1998.

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