Wafer level package with good CTE performance

Details Wafer level package with good CTE performance Wafer level package with good CTE performance

2008-06-18

2010-02-02

Clark, S. V (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S118000

Reexamination Certificate

active

07655501

ABSTRACT:
The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.

REFERENCES:
patent: 6271469 (2001-08-01), Ma et al.
patent: 6559464 (2003-05-01), Flanders et al.
patent: 6917525 (2005-07-01), Mok et al.
patent: 7349223 (2008-03-01), Haemer et al.
patent: 2007/0140627 (2007-06-01), Lu
patent: 2008/0171402 (2008-07-01), Karnezos

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