Wafer level package including ground metal layer

Details Wafer level package including ground metal layer Wafer level package including ground metal layer

2001-12-04

2003-08-19

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S701000, C257S758000, C257S781000, C257S786000, C438S612000, C438S613000

Reexamination Certificate

active

06608377

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-04245, filed on Jan. 30, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor packaging technology, and more particularly to wafer level packages.
2. Description of Related Art
Generally, semiconductor chips are packaged to carry electrical input and output signals to and from the external world and to physically protect the semiconductor chips from external environment. It has long been desired to provide low-cost semiconductor chip packages that are lighter, smaller, with higher speed, multi-function, and improved reliability. Various packaging technologies have been developed to achieve this goal. For example, a ball grid array (BGA) package provides a relatively high surface-mount density and improved electrical performance when compared with a conventional plastic package having a metal lead frame. The BGA comprises an array of minute solder balls disposed on conductive locations of a semiconductor chip. The solder balls are refluxed for simultaneous attachment and electrical communication between the semiconductor chip and conductors of a printed circuit board or other substrate. A primary difference between the BGA package and a conventional plastic package is that the electrical connection of the semiconductor chip is provided by a substrate having multiple layers with circuit patterns instead of by a lead frame as in a plastic package. The BGA package can follow the trend of ever-increasing numbers of input/output pins, greatly reduce inductive component of electrical connection, and reduce the package size to the chip scale.
Further developments from the BGA technology have created wafer level packages (WLPs). Because the WLPs adopt area array packaging concepts of the BGA packages, it is possible to make the package outline the size of the chip itself. Thus, the WLP has been an area of rapidly growing interest to the packaging community. Here the finished devices are not chip scale but rather chip size. The WLP is defined as the complete packaging of a component at the wafer level. The WLP process must provide the complete packaging solution with no additional processing at the die level either during fabrication or assembly. The WLP utilizes equipment and processes that process all dies on the wafer simultaneously during each step. A true WLP allows, for the first time, the ability to keep the cost of the IC package a relatively constant percentage of the total IC cost. Historically, with standard IC packaging technology, the cost of the package became a greater percentage of the total IC cost as the size of the semiconductor die shrinks. In some applications, the cost of individual IC packaging has exceeded the cost of the IC itself. One significant advantage of the WLP is the potential to fully integrate the function of the package with the function of the chip. Thus, power and ground distribution and global wire route or critical clocks could be accommodated with relatively thick, wide, and highly conductive copper. Such an approach can reduce pin counts on the package while either increasing performance, reducing the power requirement, or potentially both.
FIG. 1
is a partial cross-sectional view of a conventional WLP device. A plurality of semiconductor chips (not designated in the drawings) are formed in a silicon wafer
2
, and on-chip circuits are formed in each of the chips by a batch wafer fabrication process. In order to simplify the drawings, only a metal layer
3
of the on-chip circuit is shown to be formed on top of the on-chip circuit in FIG.
1
. The metal layer
3
is connected to electrode pads
4
for external interconnection of the semiconductor chip. An upper surface of the wafer
2
, i.e., an active surface of the semiconductor chip is generally covered with a passivation layer except for the electrode pads
4
. Onto the passivation layer are formed a dielectric layer
5
and a metal layer
6
, which is in contact with the exposed electrode pads
4
. An additional dielectric layer
7
is formed on the metal layer
6
. At this time, an area for external connections (e.g., solder balls
9
) remains open through the dielectric layer
7
. Through the open area of the dielectric layer
7
, solder balls
9
are electrically connected to the metal wiring
6
, so that external electrical connections for the semiconductor chip on the wafer are completed.
However, in this conventional structure, it is difficult to solve parasitic problems that occur as the frequency of electrical signals conducted by the metal wiring
6
increases. For example, the electrical performance of high-speed semiconductor chips is mainly dependent upon the design and disposition of the metal wiring
6
consisting of power lines, signal lines and ground lines. With the conventional WLP structure, it is difficult to effectively control inductance, capacitance, and parasitic elements due to the signal line and, at the same time, to guarantee the electrical performance and reliability of high-speed semiconductor IC devices.
SUMMARY OF THE INVENTION
The present invention contemplates a wafer level package assuring electrical performance and reliability of semiconductor chips operating at higher frequency.
The present invention provides a wafer level package that reduces parasitic parameters and inductance generated from signal lines.
A wafer level package of the present invention having a ground metal plate reduces the parasitic parameters and inductance generated by the signal line, and increases design discretion of signal patterns.
In an embodiment of the present invention, a wafer level package includes: (a) a semiconductor chip with an active surface including signal electrode pads, ground electrode pads, and on-chip circuits; the signal electrode pads for carrying electrical signals to and from the semiconductor chip, and the ground electrode pads for carrying ground power signal; (b) a first dielectric layer formed on the active surface to expose the signal and ground electrode pads; (c) a first metal layer formed on the first dielectric layer and including a ground metal layer in contact with the ground electrode pads, the first metal layer comprises a plate structure; (d) a second dielectric layer formed on the first metal layer and having a ground contact opening for the ground electrode pads and a signal contact opening for the signal electrode pads; (e) a second metal layer formed on the second dielectric layer and having ground and signal patterns, the ground patterns being connected to the ground electrode pads via the ground contact opening, and the signal patterns being connected to the signal electrode pads via the signal contact opening; and (f) external connections electrically connected to the ground and the signal patterns of the second metal layer and for providing an electrically conducting path for the semiconductor chip to the external world.
In another embodiment of present invention, a wafer level package further includes a third dielectric layer, a third metal layer, a fourth dielectric layer and a fourth metal layer corresponding to the first dielectric layer, the first metal layer, the second dielectric layer, and the second metal layer, respectively, overlying the semiconductor chip.
The metal layers, metal pattern layers and dielectric layers are formed in a batch wafer process for fabricating the on-chip circuits on a wafer.
These and other features and advantages will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of this invention that are not specifically illustrated.


REFERENCES:
patent: 5851911 (1998-12-01), Farnworth
patent: 6078100 (2000-06-01), Duesman et al.
patent: 6117299 (2000-09-01), Rinne et al.
patent: 6452256 (2002-09-01), Kazama et al

Affiliated with

Also associated with

Rating

Wafer level package including ground metal layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer level package including ground metal layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level package including ground metal layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3083077