Wafer level package having a side package

Details Wafer level package having a side package Wafer level package having a side package

2005-02-08

2005-02-08

Wille, Douglas (Department: 2814)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

With attachment to temporary support or carrier

C438S113000

Reexamination Certificate

active

06852607

ABSTRACT:
A method of manufacturing a wafer level package includes forming a semiconductor wafer including semiconductor chips, and forming a package body on the sides of each semiconductor chip. The package body is formed by forming a space between each semiconductor chip and potting a package material in the space, which can be a mold resin. The wafer is then separated into separate semiconductor chips by cutting through the package body.

REFERENCES:
patent: 6107164 (2000-08-01), Ohuchi
patent: 6420244 (2002-07-01), Lee
patent: 1999-0057571 (1999-07-01), None

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