Wafer-level package for micro-electro-mechanical systems

Details Wafer-level package for micro-electro-mechanical systems Wafer-level package for micro-electro-mechanical systems

2005-01-25

2005-01-25

Zarneke, David A. (Department: 2827)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Having enclosed cavity

Reexamination Certificate

active

06846725

ABSTRACT:
A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

REFERENCES:
patent: 5448014 (1995-09-01), Kong et al.
patent: 6228675 (2001-05-01), Ruby et al.
patent: 6498422 (2002-12-01), Hori
T. Nguyen Nhu et al.: “Through-Wafer Copper Plugs Formation for 3-Dimentional ICs”, DIMES, The Netherlands, pp. 141-144.
N. T. Nguyen et al.: “Through-wafer copper electroplating for three-dimensional interconnects”, Jun. 19, 2002, J. Micromech. Microeng. 12 (2002), pp. 395-399.

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