Wafer-level package for integrated circuits

Details Wafer-level package for integrated circuits Wafer-level package for integrated circuits

2007-08-28

2007-08-28

Hollington, Jermele (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

11088633

ABSTRACT:
A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

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