Wafer level package and the process of the same

Details Wafer level package and the process of the same Wafer level package and the process of the same

2003-08-13

2004-11-16

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S114000, C438S110000

Reexamination Certificate

active

06818475

ABSTRACT:

FIELD OF THE INVENTION
This present invention relates to a semiconductor package, and more specifically, to a wafer level packaging technology and the method for forming the wafer level package.
BACKGROUND
In recent progress of integrated circuit device, since the chips are manufactured by a trend of high density and it also has a trend to make semiconductor devices have smaller size in order to contain more IC in the devices. IC designers are attempted to scale down the size of devices and increase chip integration in a much smaller space. Typically, the semiconductor devices need a protection to prevent the penetration of moisture or the damage caused by accidentally damage. Owing to this, the device structure needs to be packaged by some appropriate technology. In this technology, the semiconductor dies or chips are usually packaged in a plastic or ceramic package. The package of the chips must have the function to protect the chips from being damaged and to release the heat generated by the chips while they are under operation.
The previous packaging technology was mainly on the concept of the lead frame, using the lead leg as the I/O signal exchange channel. But now, under the highly integrated requirement of the I/O signal exchange, the traditional lead frame packaging can't totally meet the demand of this requirement. Under this consideration, the packaging needs to be smaller in volume in order to meet the highly integrated requirement. Highly integrated I/O packaging concept also brings the development and a breakthrough in the package technology. A method named as ball grid array (BGA) technology is a popular used method in recent year. Integrated circuit (IC) manufacture companies tend to adapt ball grid array (BGA) technology due to the lead leg used by BGA is a ball shaped leg instead of the slender leg used by the traditional lead frame technology. Another advantages of BGA also includes that the pitches (distance between balls) are smaller and is not easily deformed because of their ball shaped legs. The smaller distances between balls reveals that the signal transportation would also become quicker than the traditional lead frame technology The U.S. Pat. No. 5,629,835, proposed by Mahulikar, et. all, which entitled “METAL BALL GRID ARRAY PACKAGE WITH IMPROVED THERMAL CONDUCTIVITY” states a ball grid array packaging method. Another U.S. Pat. No. 5,239,198 discloses a packaging form, which consists a substrate using FR4 material to form the screen printing package.
The various integrated circuit packaging have been developed in recent years, however no matter what kind it is. Most of them adapt the following procedure in dividing the wafer: First, cutting the wafer into individual chips then proceed the packaging and testing step. However, in U.S. Pat. No. 5,323,051 “SEMICONDUCTOR WAFER LEVEL PACKAGING”, it reveals a packaging step. The packaging step is conducted before cutting the wafers, it uses glass as adhesive material to seal the device in a hole. A covered hole is allowed to be the electric channel. The wafer level packaging is another manufacture trend for semiconductor package. One of the previous inventions is to form a plurality of dies on a surface of a semiconductor wafer. A glass is attached on the surface of the wafer having dies formed thereon. Then the other surface of the wafer (the surface without dies) is grinded to reduce the thickness of the wafer. This method is called back grinding. Then, the wafer is etched to separate from IC and expose a portion of the adhesive material. Another glass is attached to the wafer surface with dies by adhesive material. The next step is to form a thin film on the first glass, then etching the first glass and a portion of the adhesive material. This step is called the notch process. Thus forming a trench in the glass and adhesive material. In the next sep, Tin ball will be formed on the thin film in the subsequent process. The thin film made by solder will be patterned onto the surface of the first glass and the surface along the trench to provide an electric connection channel. Solder mask is then formed on the surface of the solder thin film surface and the surface of glass to expose the surface for which it is associated with the thin film. Tin ball is formed on the exposed solder thin film by traditional method. In the next step, the cutting procedure is conducted by etching the adhesive material in the trench to cut through the glass in order to separate the dies. The method mentioned above is complicate, it need the notch process and cutting the second glass to separate the dies. Besides, the cutting place would become a trench cliff, which is sharp for solder to attach on the cutting place and finally reduce the quality of the device in package process.
According to the reasons mentioned above, there is a need to provide a more simple and compact method to the wafer level packaging.
SUMMARY
It is an objective of the invention to provide a chip size packaging.
It is another objective of the invention to provide a wafer level package method.
It is yet another objective of the invention to provide a wafer level package method suit for the wafer level packaging test.
The wafer level package comprising: a plurality of dies forming on the wafer, and I/O metal pad forming on the first surface of the wafer.
Then, coating a photo sensitive polymer layer, for example, photo PI film is on the first surface of the wafer. Then, a portion of the photo polyimide film is removed by laser.
In the next step, coating a first photoresist on the second surface of the wafer, said second photoresist comprises a positive photoresist.
Forming a first conductive layer in the hole (opening) of the photo PI film and then covering a metal pad on the first conductive layer, wherein the first conductive layer comprises alloy with the Zn/Ni/Cu.
In the next step, forming a seeding layer with copper on the top of the first conductive layer and is on the photo sensitive polymer layer. Then, forming a second conductive layer on the circuit pattern diagram located on the defined area of the second photoresist. The second conductive layer comprises copper.
Removing the second and the first photoresist and the seeding layer covered by the second photoresist, thus forming trenches between each of the packaging entity.
Then, the filing material was filled into the trench and covering the circuit pattern diagram. The filling material comprises epoxy.
Then, executing the grinding process to grind the second surface of the wafer to expose the filling material. Next, executing an opening step to expose a portion of the circuit pattern diagram to define an area formed by the conductive convex block.
Executing a solder screen printing step to form a solder paste area, then reflowing this area to form a conductive convex block.


REFERENCES:
patent: 6607970 (2003-08-01), Wakabayashi
patent: 6656758 (2003-12-01), Shinogi et al.

Affiliated with

Also associated with

Rating

Wafer level package and the process of the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer level package and the process of the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level package and the process of the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3344213