Wafer-level package and methods of fabricating

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C438S125000, C438S611000, C438S613000, C438S615000, C438S667000, C438S680000, C438S763000, C438S780000

Reexamination Certificate

active

09832160

ABSTRACT:
A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention. Such a chip-scale package includes a semiconductor device invertedly disposed over the carrier such that bond pads of the semiconductor device substantially align with apertures formed through the carrier. Thus, the bond pads of the semiconductor device may communicate with the conductive bumps by means of the conductive material disposed in the apertures of the carrier. Methods of fabricating the carrier of the present invention and methods of fabricating chip-scale packages including the carrier are also within the scope of the present invention.

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