Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2000-06-27
2002-06-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
Reexamination Certificate
active
06400021
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer level package and method for fabricating the same, in which the packaging process is performed in an original state of a wafer before the wafer is cut.
2. Description of the Related Art
In general, the conventional wafer is firstly cut along scribe lines to be divided into individual semiconductor chips, and then various packaging processes are individually performed for the individual semiconductor chips.
However, according to the conventional way of packaging as described above, there is a problem that the semiconductor chips should be individually subjected to a large number of separate processes of packaging, which means the number of the processes is too many in consideration of the number of the semiconductor chips fabricated from a single wafer.
Therefore, there is proposed a method for fabricating a package in recent times, in which the packaging process is performed in advance in a wafer state, which means an original state of the wafer before the wafer is cut, and then the wafer after being subjected to the packaging process is cut along scribe lines. The package fabricated according to the method as described above is called a wafer level package.
FIGS. 1 and 2
show sectional views of a conventional wafer level package.
Referring to
FIG. 1
, at a surface of a wafer
1
is formed a protection layer
2
which is a silicon nitride film. A bond pad
1
a
of a semiconductor chip is disposed on the surface of the wafer
1
and is exposed through a slit formed by etching the protection layer
2
.
In this state, a lower dielectric layer
3
is applied on the upper surface of the entire protection layer
2
. Then, a portion of the lower dielectric layer
3
disposed above the bond pad
1
a
is etched to make the bond pad
1
a
be exposed. Thereafter, a metal film of copper or aluminum is vacuum-deposited on the surface of the entire construction. In this case, the metal film is deposited also on the bond pad
1
a
. Thereafter, the metal film is partially etched, so as to form a metal pattern
4
one end of which is electrically connected to the bond pad
1
a
. Thereafter, an upper dielectric layer
5
is applied on the lower dielectric layer
3
, and then is partially etched, so as to make the other end of the metal pattern
4
be exposed. The exposed other end of the metal pattern
4
functions as a ball land
4
a
on which a solder ball
6
is loaded.
Thereafter, as shown in
FIG. 2
, the solder ball
6
is loaded on the ball land
4
a
, and then is adhered to the ball land
4
a
through a reflow process by means of ultraviolet rays, so that the bond pad
1
a
of the semiconductor chip and the solder ball
6
mounted to the substrate are electrically connected to each other. Finally, the wafer
1
is cut along scribe lines drawn on the wafer
1
to be divided into a plurality of semiconductor chips. Then, the wafer level packages are completed.
The wafer level package fabricated through the process as described above operates in a state that a solder ball is mounted to its printed circuit board (PCB). In this case, the package and the board have different coefficients of thermal expansion. By this reason, when heat generated respectively in the package and in the board is exchanged between the package and the board, thermal stress is applied to the solder ball of a very small size. In result, the adhesion force of the joint by the solder ball is weakened, and in the long run the joint by the solder ball is broken to make the electric connection be broken. Likewise, it is the highest priority to ensure a reliability of the joint by the solder ball in the wafer level package.
In order to ensure the reliability of the joint by the solder ball, it is inevitable to strengthen the adhesion force between the solder ball and the ball land. However, the conventional wafer level package has a very weak adhesion force between the solder ball and the ball land, because it has a very small contact area at which the solder ball and the ball land are in contact with each other.
In more detailed description, the ball land
4
a
which is the other end of the metal pattern
4
has a circular shape, and is surrounded by the upper dielectric layer
5
, as shown in FIG.
3
. The solder ball
6
is in contact with the ball land
4
a
while being in contact with the upper dielectric layer
5
. Since the upper dielectric layer
5
is not metallically jointed to the solder ball
6
, only the flat surface of the ball land
4
a
is jointed to the solder ball
6
.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and it is an object of the present invention to provide a wafer level package and a method for fabricating the wafer level package, in which the contact area between the ball land and the solder ball is enlarged, so that the adhesion force between them is highly strengthened.
In order to achieve the above object, a wafer level package in accordance with one aspect of the present invention includes a semiconductor chip having a lower dielectric layer formed at a bond pad forming surface thereof. The lower dielectric layer includes vias and grooves, and the bond pads are exposed through the vias. A metal pattern interconnecting the bond pads and the grooves with each other is deposited on the lower dielectric layer. An upper dielectric layer is applied on the lower dielectric layer. The upper dielectric layer has a ball land through which the metal pattern deposited on a surface of the grooves is exposed. A solder ball is mounted on the ball land.
Further to the construction as described above, it is preferred that an under bump metallurgy(UBM) is formed in a ball land including the inner walls of the grooves of the upper dielectric layer, so as to reinforce the adhesion force between the ball land and the solder ball. The solder ball is mounted on the UBM. The UBM includes a conductive adhesion layer, a diffusion-preventing layer, and a solder wettable layer in order upward from the bottom. The conductive adhesion layer is a layer, which is electrically connected to the metal pattern, so as to increase the adhesion force to the metal pattern. The diffusion-preventing layer is a layer for preventing the constituent of Tin in the solder ball from permeating the adhesion layer to form metal compounds weakening the adhesion force. The solder wettable layer is a soluble layer capable of strengthening the adhesion force between the solder wettable layer and the solder ball.
Instead of the conductive adhesion layer, the metal pattern may have a construction of three stories including the conductive adhesion layer, the diffusion-preventing layer, and the solder wettable layer, likely as the conductive adhesion layer.
As follows is a method for fabricating the wafer level package having the construction as described above.
A lower dielectric layer is applied on a surface of a wafer including a plurality of semiconductor chips. The lower dielectric layer is etched so as to make the bond pads be exposed. Grooves are formed by etching portions of the lower dielectric layer spaced with a predetermined distance apart from the bond pads. A metal layer is deposited on the lower dielectric layer. The metal layer may be formed as a single layer or three-story laminated layers of the conductive adhesion layer, the diffusion-preventing layer, and the solder wettable layer. The metal layer is patterned in such a manner that there remains only the portion interconnecting the bond pads and the grooves with each other. After an upper dielectric layer is deposited on the lower dielectric layer, a portion of the upper dielectric layer on the grooves is etched, so as to form a ball land through which a portion of the metal pattern deposited on the grooves is exposed. The solder ball is mounted on the ball land, and then is firmly adhered thereto through a reflow process.
In the case where the metal layer is formed as a single layer, o
Hoang Quoc
Hyundai Electronics Industries Co,. Ltd.
Nelms David
Pillsbury & Winthrop LLP
LandOfFree
Wafer level package and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wafer level package and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level package and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2897088