Wafer level package and manufacturing method thereof

Details Wafer level package and manufacturing method thereof Wafer level package and manufacturing method thereof

2008-09-04

2010-02-16

Clark, S. V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S781000, C438S613000

Reexamination Certificate

active

07663250

ABSTRACT:
A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

REFERENCES:
patent: 6930032 (2005-08-01), Sarihan et al.
patent: 7164208 (2007-01-01), Kainou et al.
patent: 2006/0113681 (2006-06-01), Jeong et al.
patent: 2006/0246706 (2006-11-01), Ke et al.
patent: 2007/0018321 (2007-01-01), Hiatt et al.
patent: 2007/0069394 (2007-03-01), Bachman et al.
patent: 2007/0114674 (2007-05-01), Brown

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