Wafer level package

Details Wafer level package Wafer level package

1999-04-26

2001-07-31

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257S686000, C257S780000, C257S773000, C257S621000, C257S622000, C257S623000, C257S624000, C257S626000, C257S738000, C257S772000

Reexamination Certificate

active

06268642

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a wafer level package. More particularly, the present invention relates to a wafer level package having a button type of contact for engaging with a carrier.
2. Description of Related Art
Following the recent discovery of innovative fabricating techniques in the semiconductor industry, electronic devices are used in a host of electronic products. In general, the manufacturing of semiconductors can be divided into three main stages. In the first stage, a semiconductor substrate is formed. In other words, a single-crystal silicon wafer is grown using epitaxial growth techniques. Next, semiconductor devices such as MOS transistors with all the necessary metallic interconnects for linking various devices are formed. Finally, the silicon chips within the silicon wafer are cut out and then packaged. At present, the design of nearly all packages is aimed towards lighter weight, smaller thickness and installation convenience. Hence, the trend in semiconductor manufacturing is towards an increase in the level of integration, whereas the trend in packaging is to reduce package volume as much as possible. Therefore, packaging techniques such as chip scale package (CSP), multi-chip module (MCM) and chip level package (CLP) have been developed. Because the manufacturing of devices having a line width smaller than 0.18 &mgr;m is now possible, the level of integration has increased tremendously. At present, chip manufacturers are looking for packaging methods that can package a silicon chip into the smallest volume. Therefore, packages having a three-dimensional stack-up structure are now being developed. By stacking silicon chips up or stacking silicon chip packages up, overall volume of the ultimate package can be greatly reduced.
FIG. 1
is a cross-sectional view showing the stack-up structure of several integrated circuit packages according to a conventional three-dimensional package. Silicon chips
110
a
,
110
b
and
110
c
are respectively wire-bonded to their lead frames
114
a
,
114
b
and
114
c
. Next, the silicon chips and portions of the lead frames are enclosed by molding material
116
, for example, epoxy to form individual silicon chip packages
118
a
,
118
b
and
118
c
respectively. Utilizing the different degree of bending of the outer leads at the outer portions of various lead frames
114
a
,
114
b
and
114
c
, chip packages
118
a
,
118
b
and
118
c
are stacked on top of each other three-dimensionally. The outer leads of the chip package
118
c
, which lies at the bottom of the stack, are connected to the contact points of a printed circuit board
120
. This type of packaging technique is most frequently employed in tape automatic boding (TAB) package.
Although the conventional stack-up type package structure is capable of reducing volume occupation of the final package, suitable carriers (lead frame) have be used to support various silicon chips in addition to the individual or group molding operations required. Hence, not only will the thickness of individual chip packages be increased, the overall thickness of the final stacked type package will be increased as well. Furthermore, since signals to or from the conventional stacked type package must go through a longer conductive path that includes conductive wires and leads, impedance will be increased. Therefore, signal decay and signal delay will increase.
In addition, as soon as the fabrication of the integrated circuit on a semiconductor substrate is complete, a multiple of testing operations has to be carried out such as a probing test, a final test and a burn-in test. Moreover, packaging operations such as wire bonding, molding, lead forming and assembly tests must be conducted once these tests are finished. These operations not only complicate the manufacturing process, but the cost of production will increase as well.
In light of the foregoing, there is a need to provide a simpler chip packaging structure that can eliminate most of the aforementioned processing complications.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a wafer level package having button type contacts on the periphery of each package. Hence, each package can form an electrical connection with a carrier or a printed circuit board directly without using any intermediate connecting medium or having to go through complicated packaging operations. Since the traveling distance of signals will be reduced, the impedance will be reduced. Therefore signal decay and delay are prevented.
A second aspect of this invention is to provide a wafer level package whose thickness does not differ too much from the thickness of a silicon chip, thereby achieving package miniaturization.
A third aspect of this invention is to provide a wafer level package structure suitable for three-dimensional stacking.
A fourth aspect of this invention is to provide a silicon wafer having a plurality of wafer level packages. A plurality of testing circuits is formed on the scribe line sections between the packages. Moreover, the testing circuits are connected to contact points along the periphery of the packages. Consequently, there is no need to perform probe test on the wafer. The final test and the burn-in test can be carried out directly in the wafer stage, and hence testing procedures are simplified and the cost of testing is lowered.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a wafer level package. The method of forming the wafer level package comprises covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad areas. The metallic layer extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.
The silicon wafer for forming the wafer level packages having the aforementioned structure also has a number of circuits and contact points on its scribe line sections for chip testing. These testing circuits on the scribe lines can be connected to various packages via the metallic layer above the bonding pads. Alternatively, the circuits can be connected to various packages through multi-level metallic interconnects.
According to one preferred embodiment of this invention, the metallic bumps having a button shape are formed using a lead-tin alloy. The metallic bumps serve as contacting points between the wafer level package and the metallic contacts on a package carrier. Alternatively, the metallic bumps can join directly with the corresponding metallic contacts on a printed circuit board. Consequently, signal transmission path is shortened resulting in the lowering of circuit impedance. Moreover, since the layer of packaging material is deposited directly over the chip, the thickness of each package will increase just a little. Hence, thickness of the final package will not differ too much from the original wafer chip, thereby achieving package miniaturization.
In addition, this invention has button shape metallic contacts along the edge of the wafer level package. Therefore, the upper surface or the outer edge of the metallic bumps can be used as contacting areas for connecting with external circuits. The button type contact is particularly suitable for three-dimensional stacking of the wafer level packages. In t

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