Wafer-level method of hot-carrier reliability test for semicondu

Details Wafer-level method of hot-carrier reliability test for semicondu Wafer-level method of hot-carrier reliability test for semicondu

1997-11-06

2000-04-18

Ballato, Josie

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324768, 324769, 363 59, H01L 2100

Patent

active

060519843

ABSTRACT:
A wafer-level method is provided for hot-carrier reliability testing a plurality of MOS transistors formed in a semiconductor wafer. The MOS transistors in the semiconductor wafer are divided into at least three groups, including a first group, a second group, and a third group. A built-in multi-voltage supplier is integrally formed along with the MOS transistors undergoing testing in the same semiconductor wafer. This built-in multi-voltage supplier is devised in such a manner as to divide an input voltage into at least four testing voltages, including a first drain voltage, a second drain voltage, a third drain voltage, and a gate voltage. The gate voltage is connected to all of the MOS transistors undergoing testing, while the first drain voltage is connected to the drain of all of the first group of MOS transistors, the second drain voltage is connected to the drain of all of the second group of MOS transistors, and the third drain voltage is connected to the drain of all of the third group of MOS transistors. After this, the electrical characteristics under influence of the hot-carrier effects are measured. The method allows for a wafer-level testing procedure that can be performed immediately after the fabrication of the semiconductor wafer is completed. The testing procedure is also efficient and cost-effective to perform.

REFERENCES:
patent: 5426375 (1995-06-01), Roy et al.
patent: 5598009 (1997-01-01), Bui

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