Wafer level interposer

Details Wafer level interposer Wafer level interposer

1999-11-16

2002-05-21

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C324S754090

Reexamination Certificate

active

06392428

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of integrated circuits, and more particularly, to the area of wafer level testing of semiconductor chips using a wafer-interposer assembly and the manufacturing of semiconductor chip assemblies that are singulated from the wafer-interposer assembly.
BACKGROUND OF THE INVENTION
Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits,” which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect the chips with other elements of the circuit. Such substrates may be secured to an external circuit board or chassis.
The size of the chip and substrate assembly is a major concern in modern electronic product design. The size of each subassembly influences the size of the overall electronic device. Moreover, the size of each subassembly controls the required distance between each chip and other chips, or between each chip and other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limit the speed of operation of the device. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays can permit faster operations. At present, two of the most widely utilized interconnection methods are wire bonding and flip-chip bonding.
In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads disposed in a ring-like pattern around the periphery of the chip. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate.
Wire bonding ordinarily can only be employed with contacts at the periphery of the chip. It is difficult or impossible to make connections with contacts at the center of the front surface of the chip using the wire bonding approach without resulting in shorts in the wire bonding. Accordingly, the contacts on the chip must be spaced at least about 100 micrometers apart from one another. These considerations limit the wire bonding approach to chips having relatively few I/O connections, typically less than about 250 connections per chip. Moreover, the area of the substrate occupied by the chip, the wires and the contact pads of the substrate is substantially greater than the surface area of the chip itself.
Wire bonding has a number of disadvantages, for example, bond wire pads act as a scale limiter, as the pads must be of sufficient size for a proper wire bond. Furthermore, bond wires add to the conductor path length between components, increasing the impedance, inductance and capacitance of the conductors as well as the potential for cross-talk. As such, the bond wires serve to limit not only the scale of the device, but also the maximum signal frequency that can be transmitted from the chip. In some designs, these phenomena can limit the maximum speed of a chip to less than seventy percent of its potential. Thus, in some cases the chip designer must make the chip large than necessary in order to accommodate the require I/O. These and other limitations of wire bond technology have become increasingly pronounced as the market makes increasingly higher demands on the size and performance of integrated circuit devices.
In flip-chip bonding, contacts on the front surface of the chip are provided with bumps of solder. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces toward the top surface of the substrate, such that the solder bump correspond to the appropriate contact pads of the substrate. The assembly is then heated so as to liquify the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a very compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, the flip-chip bonding approach is not limited to contacts on the periphery of the chip. Rather, the contacts on the chip may be arranged in a so-called “area array” covering substantially the entire front face of the chip. Flip-chip bonding is, therefore, very well suited for use with complex chips having large numbers of I/O contacts. Unfortunately, flip-chip bonding has faced a number of problems that have limited its implementation. As one example, assemblies made by traditional flip-chip bonding can be quite susceptible to thermal stresses. The solder interconnections are relatively inflexible, and may be subjected to very high stress upon differential expansion of the chip and substrate. These difficulties are particularly pronounced with relatively large chips.
Whatever type of contact is to be made to the chip, it is necessary for the chip to be tested. Testing normally includes “burn-in” which is used to identify manufacturing defects and parametric testing which is used to verify product conformance. In the past, testing has normally taken place after the wafer has been singulated to form the individual chips, and often requiring the chips to be packaged. Thus, in the past, it was necessary to manufacture the wafer, singulate the wafer into discrete chips, package the chips and test the packaged chips individually. It is only after these steps that defective chips are identified and discarded along with the test package in some cases.
The cost of testing and packaging may be even more pronounced for chips known in the semiconductor industry as “Known Good Die” (KGD). These chips are sold unpackaged after being tested for specific levels of conformance. Typically, in order to be considered a KGD, a chip must be singulated from the wafer, packaged for testing, tested, separated from the testing apparatus and sold as a bare chip. This bare chip is then repackaged by the purchaser. This is a very inefficient, but heretofore necessary process.
Therefore, a need has arisen for an apparatus and method that provides for the attachment of an interposer to a wafer that allows full parametric testing of each of the chips on the wafer to identify good chips prior to singulation. A need has also arisen for such an apparatus and method wherein the interposer becomes part of the chip assembly that is attached to a substrate.
SUMMARY OF THE INVENTION
The present invention disclosed herein provides an apparatus and method that utilize an interposer that is attached to a wafer that allows full parametric testing of each of the semiconductor chips on the wafer to identify defective chips prior to singulation. In the present invention, the interposer, after testing of the chips, becomes part of the chip assembly that is attached to a substrate.
The present invention comprises a wafer level interposer that has a first surface and a second surface. A first pattern of electrical contact pads is disposed on the first surface. These pad correspond to a pattern of electrical contact pads disposed on a surface of a semiconductor wafer. The interposer also has a second pattern of electrical contact pads disposed on the second surface. The second pattern of electrical contact pads typically conforms to an industry-standard layout. The interposer includes a testing connector having a plurality of testing contacts that allow for testing of the individual chip but are patterned to be automatically removed during wafer singulation. A set of conductors connects the electrical contact pads on the first surface to the electrical contact pads on the s

Affiliated with

Also associated with

Rating

Wafer level interposer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer level interposer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level interposer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2854645