Wafer level integration technique

Details Wafer level integration technique Wafer level integration technique

1984-02-01

1987-10-27

Krass, Errol A.

Boots, shoes, and leggings

357 45, 365201, 437 8, G06F 1560, G11C 700

Patent

active

047034360

ABSTRACT:
Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that provide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are programmed to reassign functional circuits from a semiconductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed. Associated input and output lines are assigned in a similar manner to a correct bit position within an input and output byte.

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