Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
1999-12-22
2001-04-10
Graybill, David E. (Department: 2811)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
C438S014000, C438S015000, C438S018000, C438S129000, C438S132000, C438S467000, C438S601000, C324S765010
Reexamination Certificate
active
06214630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) manufacture technology, and more particularly, to a wafer level IC structure and a method of manufacturing this wafer level IC structure, which can help increase the yield of the IC manufacture.
2. Description of Related Art
In the semiconductor industry, IC design and fabrication is directed to high integration, high speed, high throughput, and low cost. In practice, however, 100% yield is nearly impossible, particularly for high-integration wafer level IC devices. The yield of IC manufacture is customarily defined in terms of density of defects, which can be minimized through good circuit design and the use of good repair technology. As an IC device is increased in layout size, it would also increase the probability of an increased number of defects; and therefore, the manufacture of wafer level IC devices is typically lower in yield than the manufacture of chip-sized IC devices. For wafer level memory devices, the nature yield is typically below
50
%. Especially for wafer level DRAM devices, the nature yield is much lower.
A wafer level integration circuit allows a number of chips which are of different kinds to be mounted in a single wafer, which can provide an increased level of functionality and a reduced signal transmission path for higher performance. One drawback to the wafer level integration circuit, however, is that it is highly complex in structure, resulting in low yield and high manufacture cost, and is therefore only used in some special high-level products such as supercomputers.
One solution to increase yield in the manufacture of chip-sized memory devices is to provide a redundant circuit in each memory device so that each inoperative memory cell, if any, can be replaced by a backup one in the redundant circuit. One drawback to this solution, however, is that it is only suitable for use on chip-sized IC devices and unsuitable for use on wafer level integration circuit since it would be difficult to integrate a redundant circuit in a wafer level integration circuit. Meanwhile, this solution would increase the die size so that increases the manufacturing cost. Another solution is to use the so-called discretionary wiring method, by which only operative components, excluding inoperative ones, that are checked out during testing are wired. One drawback to this solution, however, is that various photomasks, and not a single one, might be required to perform the wiring for different IC devices since different IC devices may not have inoperative components at the same locations. This drawback makes the discretionary wiring method very costly to implement.
The U.S. Pat. No. 4,703,436 discloses a wafer level IC structure for SRAM (static random-access memory) which includes a plurality of discrete memory chips and is characterized in the use of a multi-layer interconnect structure for interconnecting these discrete memory chips. Moreover, this patented structure utilizes a plurality of fuses for selective disconnection of inoperative components from active use. One drawback to this patented structure, however, is that the provision of these fuses and the use of additional test pads during testing would undesirably increase the overall layout area of the IC device and the manufacturing cost, making the resulted IC device quite bulky. Moreover, this patented structure is only suitable for SRAM fabrication but unsuitable for DRAM fabrication.
The U.S. Pat. No. 5,072,424 proposes a wafer level IC structure for DRAM, which is characterized in the use of a serial looping chain structure to interconnect the memory cells and allow these memory cells to be tested through software means. Inoperative memory cells, if any, can be replaced by logic control means through EEPROM. One drawback to this patented structure, however, is that the required refreshing process would make the operation very complex. Moreover, the use of software means for access operation would considerably slow down the access speed to the DRAM.
The U.S. Pat. No. 5,576,554 discloses a wafer level IC structure which includes a plurality of IC modules and is characterized in the use of the blank areas among the IC modules to form a chessboard-like interconnect structure serving as a bi-directional bus. Further, this patented structure is formed with a plurality of fuses at the intersections of the chessboard-like interconnect structure for selective disconnection of inoperative components, if any, from active use. This patented structure, however, is still unsatisfactory to use.
SUMMARY OF THE INVENTION
It is an objective of this invention to provide a new wafer level IC structure and a method of manufacturing this wafer level IC structure, which allows the manufacture of wafer level IC devices to have an increased yield as compared to the prior art.
It is another objective of this invention to provide a new wafer level IC structure and a method of manufacturing this wafer level IC structure, which allows the manufacture process to be more cost-effective to implement than the prior art.
It is still another objective of this invention to provide a new wafer level IC structure and a method of manufacturing this wafer level IC structure, which allows the resulted IC device not to be increased in signal transmission distance so as to ensure high performance.
It is yet another objective of this invention to provide a new wafer level IC structure and a method of manufacturing this wafer level IC structure, which can help increase the packing density and number of I/O points as compared to the prior art.
It is still yet another objective of this invention to provide a new wafer level IC structure, which can provide two manufacturing processes for two kind products respectively: one is a normal single-die package IC; the other is a wafer level IC, according to the market demand.
In accordance with the foregoing and other objectives, the invention proposes a new wafer level IC structure and a method of manufacturing this wafer level IC structure.
The wafer level IC structure of the invention includes (a) a semiconductor wafer; (b) a plurality of discrete IC blocks defined on the wafer, each IC block including: (b1) a plurality of IC components and backup components; (b2) a multi-layer interconnect structure for electrically interconnecting the IC components in the associated IC block; (b3) a first set of bonding pads which are electrically connected to the multi-layer interconnect structure and serve as external connecting points for the IC components in the associated IC block; (b4) a first set of test pads which are electrically connected to the IC components and the multi-layer interconnect structure for use during testing; and (b5) a first set of fuses which are electrically connected to the IC components and the multi-layer interconnect structure for use to selectively disconnect the associated IC components from active use if the associated IC components are determined to be inoperative during testing; (c) a redistribution line structure including a plurality of redistribution lines which are electrically connected to the first set of bonding pads of each of the IC blocks in a predefined manner so as to functionally combine the discrete IC blocks into an integral functional unit; (d) a second set of test pads which are electrically connected to the IC blocks and the redistribution line structure for use to apply test signals to the IC blocks during testing; and (e) a second set of fuses which are electrically connected to the redistribution line structure for use to selectively disconnect the associated IC blocks if the associated IC blocks are determined to be inoperative during testing.
In terms of method, the invention includes the following procedural steps: (Step
1
) preparing a semiconductor wafer; (Step
2
) defining a plurality of discrete IC blocks on the wafer; (Step
3
) forming a plurality of IC components and backup components in each of the IC blocks; (Step
4
) performing a first metallizatio
Feng Taisheng
Han Charlie
Hsuan Min-Chih
Graybill David E.
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
LandOfFree
Wafer level integrated circuit structure and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wafer level integrated circuit structure and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level integrated circuit structure and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2527426