Wafer level I/O test, repair and/or customization enabled by...

Details Wafer level I/O test, repair and/or customization enabled by... Wafer level I/O test, repair and/or customization enabled by...

2011-03-22

2011-03-22

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

Reexamination Certificate

active

07913202

ABSTRACT:
A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.

REFERENCES:
patent: 7117469 (2006-10-01), Dahl
patent: 7402897 (2008-07-01), Leedy
patent: 2001/0013114 (2001-08-01), LaBerge
patent: 2004/0187087 (2004-09-01), Eneboe et al.
patent: 2005/0240892 (2005-10-01), Broberg et al.
patent: 2005/0262465 (2005-11-01), Goyal
patent: 2008/0237591 (2008-10-01), Leedy

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