Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2006-03-14
2008-11-11
Kebede, Brook (Department: 2894)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S612000, C257SE21511
Reexamination Certificate
active
07449365
ABSTRACT:
Forming a wafer level chip scale flip chip package includes determining isolation requirements of an integrated circuit formed in a semi conductive substrate from package signal connections of the wafer level chip scale flip chip package. Operation may further include, based upon the integrated circuit characteristics, selecting a thickness of at least one dielectric layer isolating a top metal layer of the integrated circuit from the package signal connections of the wafer level chip scale flip chip package, determining a minimum pitch of the package signal connections of the wafer level chip scale flip chip package, and determining a maximum lateral distance from the signal pad to a servicing package signal connection of the wafer level chip scale flip chip package and determining a position of the servicing package signal connection of the wafer level chip scale flip chip package based upon the maximum lateral distance.
REFERENCES:
patent: 5534465 (1996-07-01), Frye et al.
patent: 5728606 (1998-03-01), Laine et al.
Behzad Arya (Reza)
Chen Henry K.
Kaufmann Matthew Vernon
MacIntosh Malcolm
Rael Jacob Jude
Broadcom Corporation
Garlick Bruce E.
Garlick & Harrison & Markison
Kebede Brook
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