Wafer level device package with sealing line having...

Details Wafer level device package with sealing line having... Wafer level device package with sealing line having...

2011-03-22

2011-03-22

Dickey, Thomas L (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257SE23061, C257SE33056

Reexamination Certificate

active

07911043

ABSTRACT:
Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

REFERENCES:
patent: 5608264 (1997-03-01), Gaul
patent: 6452238 (2002-09-01), Orcutt et al.
patent: 6972480 (2005-12-01), Zilber et al.
patent: 2003/0068847 (2003-04-01), Watanabe et al.
patent: 2003/0230798 (2003-12-01), Lin et al.
patent: 2004/0087043 (2004-05-01), Lee et al.
patent: 2006-69312 (2006-03-01), None

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