Wafer level decal for minimal packaging of chips

Details Wafer level decal for minimal packaging of chips Wafer level decal for minimal packaging of chips

1996-11-04

1999-08-31

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

438106, 438118, H01L 2144, H01L 2148, H01L 2150

Patent

active

059465557

ABSTRACT:
The invention includes the use of a decal to produce a packaged chip either at the chip level or wafer level. The decal includes a substrate containing circuitry that routes the chip output pads to bumps prepared for package attachment to another substrate such as a printed circuit board. The decal can be applied either to the wafer or to a single chip. The decal protects the chip and if necessary changes the interconnection density so that the chip can be interfaced with a printed circuit board or other electronic device. This configuration also may allow the packaged integrated circuit to be tested utilizing the bumps on the decal as temporary electrical contact features.

REFERENCES:
patent: 5207887 (1993-05-01), Crumly et al.
patent: 5422313 (1995-06-01), West
patent: 5521122 (1996-05-01), Kuramochi
patent: 5658827 (1997-08-01), Aulicino et al.

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