Wafer level CSP packaging concept

Details Wafer level CSP packaging concept Wafer level CSP packaging concept

2011-05-10

2011-05-10

Roman, Angel (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S435000, C257S787000, C257S788000, C257SE23117

Reexamination Certificate

active

07939916

ABSTRACT:
An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.

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http://www.fujitsu.com/downloads/micro/fma/pdf/supercsp.pdf “Super CS”. Fujitsu Microelectronics America, Inc. pp. 17-19.

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