Wafer level contact sheet and method of assembly

Details Wafer level contact sheet and method of assembly Wafer level contact sheet and method of assembly

1997-12-09

2001-11-06

Gaffin, Jeffrey (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S262000

Reexamination Certificate

active

06313411

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). More specifically, the present invention relates to a burn-in system that includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers who make integrated circuit chips begin by manufacturing semiconductor wafers. Each wafer is typically 100 mm, 125 mm, 150 mm, 200 mm or 300 mm in diameter and contains anywhere from one to several thousand chips or die on the wafer. When manufacture of the wafer is completed, chips or die are cut or “diced” from the wafer and may later be mounted into single chip or multiple chip packages for implementation in a printed circuit board or other applications.
When manufacture of a wafer is completed, it is customary practice to test each chip on the wafer to determine whether each chip, as manufactured, electrically matches design criteria, matches performance criteria of the system in which the chip is to be implemented, and will be reliable in operation. If a chip fails electrical testing or reliability testing, the chip is not suitable for implementation in a system without repairing the chip or exercising redundancy features which may have been designed into the chip. Performance testing of chips may be used to speed sort chips into different categories suitable for different applications and sale at different prices.
Reliability testing is used to screen out chips having an undesirable short life span. Typically, a significant percentage of a group of chips will fail early in their lifetime due to marginal conditions during manufacture. Subsequently, a very low percentage of the group will fail during an extended period of use of the chips. Reliability screening of semiconductor chips is typically performed by a process of supplying test signal patterns to chips under test to repeatedly stimulate all devices and wires on a chip, and is typically performed at elevated temperatures to simulate the first six months of operation. Therefore, the screening procedure is known as burn-in.
Burning in chips tends to induce accelerated failures. Two examples of such failures are contamination induced failure at via interfaces, and gates and junctions, and in metal wires malformed during manufacture which may neck down to very thin regions on the order of 50% of the design width, which varies by technology and time but, is presently 0.35 &mgr;m. The metal in these necked down regions will tend to drift in the direction of electrical current flow by a mechanism known as electromigration, where the rate of drift is directly proportional to current density, accelerated by elevated temperature. Upon sufficient electromigration, an open circuit condition will occur in the necked down region of the metal and cause a logical failure of the chip for some test signal patterns. Gate oxide regions where transistors are formed using FET transistor technology are also a frequent source of reliability failure. The thickness of a gate oxide region of a transistor must be controlled within exacting tolerances. If the gate oxide region of one or more transistors on a chip, as manufactured, is too thin, the gate oxide may break down due to high electric fields within the transistor when test patterns are applied to the chip. Upon failure, output from the test patterns will evidence a failure.
While very valuable, the process of burn-in has historically been time consuming and expensive for semiconductor manufacturers. Existing burn-in is typically performed on integrated circuits at temperatures between 90° C. to 125° C., for anywhere between 24 to 168 hours. Obviously, this slow rate of reliability testing impedes volume production of functional semiconductors and adds tremendous cost.
Many manufacturers have attempted to address low throughput of known burn-in processes by creating burn-in boards onto which many diced chips are placed in chip packages, and then the packages go into sockets on the burn-in boards. Thereafter, each chip on the test board is simultaneously exercised with test patterns at elevated temperatures. Thus, many chips are burned-in at once. These systems effectively reduce the time required to burn-in a large volume of chips. However, the added cost of packaging defective or unreliable die is a significant shortcoming of such known burn-in processes.
Bare die burn-in (BDBI) is required to provide Known Good Die (KGD) determinations for multi-chip module's (MCM's) and other bare die applications, such as, chip-on-board (COB). Without bare die burn-in, yield of MCM's (and other bare die applications) is severely impaired, resulting in higher product costs. Current BDBI is typified by the Texas Instrument's “Die Mate”® product where a bare die is placed into a temporary package and the burn-in test is performed. The required alignment and handling steps in this procedure add cost, process complexity, and time to provide bare dies that will be reliable or “Known Good.”
Another technique for improving throughput of the burn-in process is to perform burn-in on whole or parts of whole wafers containing undiced integrated circuits or chips. This process is known as wafer level burn-in (WLBI). In wafer level burn-in, electrical terminals from a test apparatus are brought into intimate contact with contact pads of one or more chips. It is therefore less destructive than soldering chips to a burn-in board. However, problems of planarity of electrical terminals of the test apparatus and with mismatch between the coefficient of thermal expansion of the test apparatus and the wafer under test exist.
These problems have been addressed to date by several different techniques. For example, the industry uses a material known as CIC which is a high pressure, high temperature, lamination of copper on the outside of an interior INVAR sheet. One of the drawbacks with this material is that the maximum thickness it can obtain is in sheets that are 62 mils thick. A second drawback is that when CIC is manufactured, it is rolled on a big spool. As a result, material from the outside of the spool to the inside of the spool has a different plastic deformation and hence radius of curvature.
Another drawback with the rolled CIC is that in order to get the desired thickness and planarity, four pieces of CIC must be laminated together. There must be an even number of CIC layers because two layers may be curved down and one may be curved up. This results in an over balance in one direction or the other. So the number of CIC sheets must be an evennumber—2, 4 or 6. The drawback of using so many sheets of CIC is that since CIC is very dense, the thicker the base, the heavier it becomes.
Another disadvantage of the CIC system is that, as manufactured, there is an individual piece of copper on both sides of the INVAR 36 going through a lamination process through rollers. The thickness of the copper top to bottom changes. As a result of the different thicknesses, stress differential warpage from top to bottom occurs, which is very detrimental during thermal excursions. The thickness of the CIC could change as you go through the process also. You cannot machine down the CIC to a uniform thickness because you may machine off more on one side than the other.
Another disadvantage of the CIC system is that the material having the highest coefficient of thermal expansion (CTE), the copper, is on the outside. Thus, greater stress is generated with CIC.
One technique that is used to contact a wafer employs electrical terminals, such as S shaped probes or Pogo® pins. With S shaped bendable wire probes, the test apparatus is br

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