Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1996-11-08
1998-06-16
Niebling, John
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
438613, 438118, H01L 2166, H01L 2144
Patent
active
057669791
ABSTRACT:
The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
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Pending U.S. patent application Ser. No. 08/724,393, filed Oct. 1, 1996, entitled "A Reusable, Selectively Conductive, Z-Axis, Elastomeric Composite Substrate".
Genco, Jr. Victor M.
Lebentritt Michael S.
Niebling John
W. L. Gore & Associates, Inc.
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