Wafer level chip size package having redistribution layers

Details Wafer level chip size package having redistribution layers Wafer level chip size package having redistribution layers

2011-07-12

2011-07-12

Williams, Alexander O (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257SE29325, C257SE23023, C257SE23124, C257SE23069, C257S737000, C257S738000

Reexamination Certificate

active

07977783

ABSTRACT:
A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer. After forming a first under bump metallurgy (UBM) layer on the land, a solder ball is reflowed to the first UBM layer. A second UBM layer is widely formed on the entire second dielectric layer that is the outer circumference of the first UBM layer and is connected to the redistribution layer through a via-hole. Therefore, the second UBM layer having a large area can be used as a ground plane or a power plane. In addition, the second UBM layer can electrically connect the redistribution layers physically separated from each other. Therefore, the plurality of redistribution layers can cross each other without being electrically shorted with each other.

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