Wafer level chip scale packaging structure and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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C257S734000, C257SE23021, C438S106000

Reexamination Certificate

active

08039935

ABSTRACT:
A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

REFERENCES:
patent: 4948456 (1990-08-01), Schubert
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5925931 (1999-07-01), Yamamoto
patent: 5977632 (1999-11-01), Beddingfield
patent: 6023103 (2000-02-01), Chang et al.
patent: 6277669 (2001-08-01), Kung et al.
patent: 6407459 (2002-06-01), Kwon et al.
patent: 6441487 (2002-08-01), Elenius et al.
patent: 6555908 (2003-04-01), Eichelberger et al.
patent: 6621164 (2003-09-01), Hwang et al.
patent: 6806570 (2004-10-01), Lee et al.
patent: 6818544 (2004-11-01), Eichelberger et al.
patent: 6998718 (2006-02-01), Chang et al.
patent: 2002/0100982 (2002-08-01), Kim et al.
patent: 2002/0127768 (2002-09-01), Badir et al.
patent: 2004/0043538 (2004-03-01), Lo et al.
patent: 2005/0104226 (2005-05-01), Chang et al.
Hamano et al., “Super CSP™: WLCSP Solution for Memory and System LSI,” International Symposium on Advanced Packaging Materials, 1999, pp. 221-225.
Kazama et al., “Development of Low-cost and Highly Reliable Wafer Process Package,” Electronic Components and Technology Conference, 2001, 7 pages.

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