Wafer level chip scale packaging structure and method of...

Details Wafer level chip scale packaging structure and method of... Wafer level chip scale packaging structure and method of...

2005-06-15

2008-01-15

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S107000, C438S118000

Reexamination Certificate

active

07319050

ABSTRACT:
A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will peel or the sacrificial layer material will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

REFERENCES:
patent: 4948456 (1990-08-01), Schubert
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5925931 (1999-07-01), Yamamoto
patent: 6023103 (2000-02-01), Chang et al.
patent: 6407459 (2002-06-01), Kwon et al.
patent: 6621164 (2003-09-01), Hwang et al.
patent: 6806570 (2004-10-01), Lee et al.
patent: 2002/0127768 (2002-09-01), Badir et al.
Hamano et al., “Super CSP™: WLCSP Solution for Memory and System LSI,” International Symposium on Advanced Packaging Materials, 1999, pp. 221-225.
Kazama et al., “Development of Low-cost and Highly Reliable Wafer Process Package,” Electronic Components and Technology Conference, 2001, 7 pages.

Affiliated with

Also associated with

Rating

Wafer level chip scale packaging structure and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer level chip scale packaging structure and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level chip scale packaging structure and method of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3962640