Wafer level chip scale packaging structure and method of...

Details Wafer level chip scale packaging structure and method of... Wafer level chip scale packaging structure and method of...

2006-02-14

2006-02-14

Clark, S. V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S780000

Reexamination Certificate

active

06998718

ABSTRACT:
A wafer level chip scale packaging structure and the method of fabricating the same are disclosed to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the PCB is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the PCB will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

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Kazama et al, “Development of Low-cost and Highly Reliable Wafer Process Package” Electronic Components and Technology Conference, 2001, 7 pages.

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