Wafer level chip scale package and process of manufacture

Details Wafer level chip scale package and process of manufacture Wafer level chip scale package and process of manufacture

2011-06-07

2011-06-07

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S113000, C438S460000, C257SE23061

Reexamination Certificate

active

07955893

ABSTRACT:
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

REFERENCES:
patent: 6133634 (2000-10-01), Joshi
patent: 6355502 (2002-03-01), Kang et al.
patent: 6469384 (2002-10-01), Joshi
patent: 6646329 (2003-11-01), Estacio et al.
patent: 6653740 (2003-11-01), Kinzer et al.
patent: 6767820 (2004-07-01), Standing et al.
patent: 2003/0052405 (2003-03-01), Moriguchi
patent: 2003/0067071 (2003-04-01), Cardwell
patent: 2003/0207546 (2003-11-01), Wajima
patent: 2008/0274603 (2008-11-01), Do et al.
patent: 09-129867 (1997-05-01), None
patent: WO 01-75961 (2001-10-01), None
PCT International Search Report dated Jul. 27, 2009 for International Patent Application No. PCT/US2009/032242.

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