Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2009-02-17
2010-11-30
Geyer, Scott B (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
07842543
ABSTRACT:
A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.
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Feng Tao
Liu Yan
Wu Ruisheng
Alpha and Omega Semiconductor Incorporated
Cai Jingming
Geyer Scott B
Schein & Cai LLP
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