Wafer level chip scale package and manufacturing method for...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond

Reexamination Certificate

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Reexamination Certificate

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07446422

ABSTRACT:
Disclosed are a wafer level chip scale package and a method for manufacturing the same. An RDL is formed on a semiconductor die through a sputtering process, and a UBM is formed on the RDL through an electroplating process by using the RDL as a seed layer. Thus, the RDL sputtering, UBM electroplating, RDL etching and leakage descum processes are carried out only one time, thereby simplifying the structure and manufacturing processes of the package. Since a copper layer of the RDL is formed with a relatively large thickness through the sputtering process, current density is uniformly distributed during the electroplating process, so it is possible to uniformly form the thickness of the UBM by using pure nickel.

REFERENCES:
patent: 6400021 (2002-06-01), Cho
patent: 6492198 (2002-12-01), Hwang
patent: 6689678 (2004-02-01), James et al.
patent: 6750135 (2004-06-01), Elenius et al.
patent: 2004/0245630 (2004-12-01), Huang et al.
patent: 2006/0038291 (2006-02-01), Chung et al.
patent: 2006/0125110 (2006-06-01), Do et al.
patent: 2006/0270108 (2006-11-01), Farnworth et al.

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