Wafer level chip-scale package

Details Wafer level chip-scale package Wafer level chip-scale package

2003-03-04

2004-03-30

Fahmy, Wael M. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C257S737000, C257S778000, C257S784000

Reexamination Certificate

active

06713870

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer level chip-scale package, more specifically, to a package employing under bump metallurgies as bonding pads for the wire bonding process.
2. Description of the Related Art
IC technology has forged ahead in the past decade to satisfy the requirements of fast transmitting speed, excellent heat dissipation, smaller overall sizes and lighter weight. With these goals in mind, many IC engineers have developed wafer level chip-scale packages to take full aforementioned advantages and have other merits, such as a lower manufacturing cost and overall package dimensions substantially equal to that of a chip enclosed within the package.
FIG. 1
is a diagrammatic top view of the bonding pad layout of a conventional chip. A chip
10
comprises a plurality of bonding pads
11
which are distributed and arranged around the chip
10
. From the disclosure of the wafer level chip-scale packaging technique, a metal layer is further formed on the surface of the chip
10
, and the pads
11
are reconnected to corresponding bump pads from the periphery toward the center of the chip (not shown). The corresponding manufacturing process is referred to in the I/O pad (or bonding pads) redistribution technique.
FIG. 2
is a diagrammatic top view of the I/O pad redistribution layout of a conventional chip. Also referring to
FIG. 3
showing a cross-sectional view of
FIG. 2
, a metal circuit layer is provided on a bonding pad
33
and a passivation layer
32
of a chip
20
, wherein the metal circuit layer individually form metal pads
22
on each of peripheral bonding pads
33
. The metal pad
22
is electrically connected to a bump pad
23
through a connection trace
21
. In almost all embodiments, the bump pad
23
is arranged in a matrix configuration.
As shown in
FIG. 3
, the metal circuit layer is overlaid with a resilient passivation layer
31
thereon, wherein the resilient passivation layer
31
has resilient holes. Each bump pad
23
is associated with one of the resilent hole to expose itself therein. Finally, the bump pad
23
is needed to bump a solder ball or electroplate a copper rod as a contact with a flip-chip substrate (not shown), and the resilient passivation layer
31
can absorb and suppress the mechanical stress induced from the flip-chip substrate.
As shown in
FIG. 2
, a higher trace density in the metal circuit layer is accompanied with an increased number of bonding pads
33
on a same chip. That is, the width and pitch of connection traces
21
are reduced so that the trace layout on redistribution processes is more difficult than before. In some practical cases, the connection trace
21
is required to have a circuitous route to accomplish the redistribution of the bonding pad
33
. Because there are a lot of limitations for the circuit in high-speed signal transmission, such as impedance match, self-inductance, cross-inductance and cross talk, the trace layout based on these complex considerations are considered as try and error procedure in design.
FIG. 4
is a diagrammatic partial view of the circuit in accordance with conventional bonding pad redistribution. A metal pad
411
is electrically connected to a bump pad
421
located at an inner area through a connection trace
431
, and a metal pad
412
is also electrically connected to a bump pad
422
adjacent to the bump pad
421
through the connection trace
432
. Because each of the contacts of the flip-chip substrate is well assigned with an electrical function, the metal pad
411
cannot be electrically connected to the bump pad
422
on the shortest route. Furthermore, due to the limitation of the entire metal circuit layer being on a same plane surface, the connecting circuit
431
travels through a circuitous route between the bump pad
422
and
423
to reach the bump pad
421
.
SUMMARY OF THE INVENTION
The main object of the present invention is to provide a wafer level chip-scale package employing a metal wire to go across some connection traces from a metal pad and reach a bump pad in order to decrease the complexity of the circuit layout under a redistribution consideration.
The second object of the present invention is to provide a wafer level chip-scale package, which can shorten the routes of corresponding connection traces through by the replacements of metal wires to improve the electrical characteristics of the package on performance.
To achieve the foregoing objects of the present invention, a wafer level chip-scale package is disclosed. A chip includes a plurality of metal pads individually formed on each of the bonding pads. In the same metal circuit layer where metal pads exist, bump pads are arranged in a matrix configuration, wherein almost all of them are electrically connected one by one to bonding pads through connection traces. Bump pad isolated by lacking connection trace have an extension portion of itself, and the resilient passivation layer does not overlay the bump pad and extension portion. There is a metal wire used to connect the extension portion of the bump pad with the corresponding metal pad, which is also not overlaid by the resilient passivation layer. Therefore, the metal wire can directly cross over other connection traces to achieve the electrical connection on a shorter route.


REFERENCES:
patent: 6287893 (2001-09-01), Elenius et al.
patent: 6300234 (2001-10-01), Flynn et al.
patent: 6429532 (2002-08-01), Han et al.
patent: 6501169 (2002-12-01), Aoki et al.

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