Wafer-level chip scale package

Details Wafer-level chip scale package Wafer-level chip scale package

1999-02-11

2001-03-20

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S778000, C257S787000, C257S723000, C257S775000

Reexamination Certificate

active

06204562

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor packaging structure, and more particularly, to a structure of wafer-level chip scale package (CSP).
2. Description of the Related Art
As the technology of semiconductor fabrication grows more and more advanced, the relevant techniques have to be further developed to coordinate the requirements of the semiconductor devices. The fabrication process of a semiconductor device typically includes three stages. In the first stage, an epitaxy technique is used for the formation of a semiconductor substrate. Semiconductor devices such as metal-oxide semiconductor (MOS) and multilevel interconnection are fabricated on the substrate in the second stage. The third stage is the packaging process. It is now a leading trend for fabricating a device or an electronic product with a thin, light, and small dimension, that is, with a higher integration for semiconductor devices. In terms of packages, many techniques such as chip scale package, multi-chip module (MCM) have been developed to obtain a high integration. The development of the fabrication technique with a line width of 0.18 &mgr;m has evoked a great interest and intensive research to further decrease the package volume. It is thus one of the very important package techniques to arrange more than one chips into a single package. In a multi-chip package, chips of processor, memory, including dynamic random access memory (DRAM) and flash memory, and logic circuit can be packed together in a single package to reduce the fabrication cost and the packaging volume. Furthermore, the signal transmission path is shortened to enhance the efficiency. The multi-chip IC packaging technology may also be applied to a multi-chip system with variable functions and operation frequencies, for example,
1. A system comprises memory chips, microprocessors, resistors, capacitors, and inductors.
2. A system comprises memory chips (DRAM), logic circuit chips, and memory chips (Flash memory),
3. A system comprises analog chips, logic circuit chips, memory chips (including DRAM, SRAM, Flash memory), resistor, capacitor, and inductor.
In
FIG. 1
, a conventional dual-chip module is shown. A substrate
10
comprising a copper pattern
12
is provided. By means of the formation of solder balls
14
, the electrical connection to an external device or circuit is established. A very popular material of the substrate is polymide. A die
16
with a larger size is adhered onto the substrate
10
with an insulating layer
16
as a glue layer in between. An insulating layer
20
and a die
22
with a smaller size is then disposed on the insulating layer
16
. Conductive wires
24
are formed to electrically connect the dies
18
,
22
and the substrate
10
. Using resin
26
, the dies
18
and
22
and the substrate
10
are molded. The electrical connection between the whole package and a printed circuit board can be achieved by ball grid array (BGA) which use solder balls
14
to connect the terminals on the printed circuit board. The drawback of this conventional dual-chip module includes a large surface is occupied since dies are packaged on a same side of surface. The thickness of the package is as thick as 1.4 mm, therefore, the volume of the package is large, and the signal transmission path between chips is long.
To further shrink the volume of package, a face to face multi-chip package is disclosed in U.S. Pat. No. 5,331,235. This multi-chip package uses tape automatic bonding technique. The electrical connection between chips and printed circuit board is achieved by the installation of a lead frame or other carriers. The signal transmission path is lengthened. In addition, a large thickness and surface area are resulted by using the molding material (resin) of package. The applicability is reduced, and the heat dissipation is not effective. Moreover, this kind of package can not be applied to high frequency products.
SUMMARY OF THE INVENTION
The invention provides a wafer-level chip scale package. Flip chip technique is adapted for connecting dies without using a carrier. Thus, the volume occupied by the carrier in the conventional structure is saved. The molding material is only infilled into the spaces between the dies, that is, a bare wafer molding type is used. The size of the package is thus further reduced. More specifically, the thickness of the package is approximately the same as the total thickness of the dies packed into the package, and the surface area of the package is about the same of that of the die with a larger surface area in the package.
In addition, using the application of flip chip technique to achieve the electrical connection between the dies does not require the formation of any additional bonding wires or other conductive paths. The electrical connection between the dies and an external device or circuit can be performed by the bumps formed on the larger die in the package. Thus, a short and direct signal transmission path is provided to enhance the performance of the chips.
Moreover, since a bare wafer molding type is used, the wafer-level chip scale package mentioned above has an enhanced performance of heat dissipation.
To achieve the above-mentioned objects and advantages, a wafer-level chip scale package is provided. The package comprises at least a larger die and a smaller die compared to each other in size. The larger die comprises a pad redistribution layer and bumps formed on a peripheral region of the pad redistribution layer. The smaller die is adhered onto a central region of the pad redistribution layer of the larger die by flip chip technique. The package further comprises a molding material infilled between the larger and the smaller dies and covering one side of each of the dies, with one end of the bumps exposed. Solder balls are then formed on the exposed end of the bumps. The fixture of the package is enhanced by the molding material.
In an embodiment which is to be introduced in more details in the following paragraphs, solder balls or bumps are formed on the pad distribution. The electrical connection between the larger die and the smaller die can be achieved by the formation of these solder balls or the bumps. These solder balls are typically very small in size and negligible. Thus, the resultant thickness is not increased thereby.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5760478 (1998-06-01), Bozso et al.
patent: 5790384 (1998-08-01), Ahmad et al.
patent: 5798567 (1998-08-01), Kelly et al.
patent: 5804882 (1998-09-01), Tsukagoshi et al.
patent: 5869894 (1999-02-01), Degani et al.
patent: 5939783 (1999-08-01), Laine et al.
patent: 5977640 (1999-11-01), Bertin et al.
patent: 5-129516 (1993-05-01), None

Affiliated with

Also associated with

Rating

Wafer-level chip scale package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer-level chip scale package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer-level chip scale package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2548074