Wafer-level chip package process

Details Wafer-level chip package process Wafer-level chip package process

2006-08-15

2009-06-02

Zameke, David A (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C257SE21599

Reexamination Certificate

active

07541218

ABSTRACT:
A wafer-level chip package process is provided. First, a transparent substrate having a chip sealing layer and a transparent layer is provided. Then, the chip sealing layer is cut to form a first groove of a predetermined depth, and an adhesive is formed on the chip sealing layer. Next, a wafer having a back surface and an active surface is provided, and the transparent substrate is disposed on the active surface of the wafer, wherein the chip sealing layer is adhered to the active surface by the adhesive. Next, the transparent layer is cut to form a second groove corresponding to the first groove. Next, the back surface of the wafer is cut to form a third groove corresponding to the first groove. After that, the wafer and the transparent substrate are singulated to form a plurality of chip package structures.

REFERENCES:
patent: 7190039 (2007-03-01), Boettiger et al.
patent: 7247509 (2007-07-01), Yamauchi et al.
patent: 7306975 (2007-12-01), Harris, Jr.
patent: 7419840 (2008-09-01), Omori
patent: 2006/0051887 (2006-03-01), Yamamoto et al.

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