Wafer-level burn-in testing of integrated circuits

Details Wafer-level burn-in testing of integrated circuits Wafer-level burn-in testing of integrated circuits

1989-08-23

1991-09-10

Wieder, Kenneth A.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324158D, 324158P, 437 8, 357 45, G01R 100, G01R 3102

Patent

active

050477110

ABSTRACT:
A wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, is so constructed as to enable burn-in testing of the integrated circuits while they are still in the wafer. In this wafer, individual integrated circuits of the array include contact pads that extend into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer. A system for testing such a wafer includes a testing station for applying and monitoring burn-in test signals for individual integrated circuits; and contact probes for coupling the testing station to the contact pads for a plurality of the individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for a plurality of the individual integrated circuits while they are contained in the wafer. Control means are coupled to the testing means for discontinuing the application of burn-in test signals to a given individual integrated circuit when the monitored test signals for the given integrated circuit indicate that the given integrated circuit has failed the burn-in test.

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