Wafer-level burn-in oven

Details Wafer-level burn-in oven Wafer-level burn-in oven

2001-03-20

2003-04-22

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S1540PB

Reexamination Certificate

active

06552560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to apparatus and method for burn-in testing of integrated circuits and semiconductors at the wafer level.
2. Description of the Related Art
Semiconductor manufacturers make integrated circuit chips in batch on what is typically referred to as wafers or semiconductor wafers. These wafers are generally flat circular disks, between 100 millimeters to 300 millimeters or greater in diameter and may contain one to upwards of several hundred integrated circuit chips. When manufacture of the wafer is completed, the individual chips or die are cut or “diced” from the wafer and are later mounted into single chip or multiple chip packages for implementation in a printed circuit board or other application for electronic uses.
It is customary practice to test each chip, either individually or as part of a multiple chip package to determine if each chip as manufactured, electrically matches design criteria, matches performance criteria of a system in which the chip is to be implemented, and will be reliable in operation. If a chip fails reliability testing, the chip is not suitable for implementation in a system without repairing the chip or exercising redundancy features which may have been designed into the chip.
The integrated circuit chips are assembled into packages for protection and convenience in handling as well as for further assembly into equipment. These latter processing stages contribute a major portion of the manufacturing cost of the finished products utilizing semiconductor chip. If failure is detected after the chips are packaged, significant costs can be incurred due to failure of electronic systems into which the multiple chip packages are incorporated. Thus, before packaging, integrated circuit chips must be tested thoroughly.
Performance testing of chips is used to speed-sort chips into different categories suitable for different applications and sale at different prices. Reliability testing is used to screen out chips having an undesirably short life span. Typically, a significant percentage of a group of chips will fail early in their lifetime due to marginal conditions during manufacture. Subsequently, a very low percentage of the group will fail during an extended period of use of the chips. Reliability screening of a semiconductor chip is typically performed by a process of supplying test signal patterns to chips under test to repeatedly stimulate all devices and wires on a chip, and is typically performed at elevated temperatures to simulate the first six months of operation. This screening process is commonly referred to as burn-in or burn-in testing.
Burning in chips tends to induce accelerated failures. While very valuable, the process of burn-in has historically been time consuming and expensive for semiconductor manufacturers, particularly if testing is performed on individual chips or after chips are incorporated into a package. Existing bum-in is typically performed on integrated circuits at temperatures between 90° C. to 125° C., for anywhere between 24 to 168 hours. Obviously, this slow rate of reliability testing impedes volume production of functional semiconductors and adds tremendous cost. Generally, manufacturers have attempted to reduce these costs by burn-in testing of semiconductor wafers at the wafer level.
In wafer level burn-in, electrical terminals from a test apparatus or test board are brought into contact with contact pads of the individual chips on a semiconductor wafer to test the chips for electrical performance. The wafer is typically mounted in a wafer chuck, a holder for the wafer, having electrical probes or pins that align with contact pads of the integrated circuit chips on the wafer. Through the use of automatic computerized testing, power sources provide required test voltages and electronic signals for communication between the integrated circuit chips of the wafer and the computerized test equipment. The equipment automatically records the results for all of the integrated circuit chips on the wafer. The number, sequence, and types of test specified have been programmed into the equipment, and the test is carried out generally without operator assistance. The equipment records the characteristics of all integrated circuit chips tested, passes as well as failures, by wafer and production lot. Rejects are marked with a visible ink spot for identification, and some equipment also generates maps of the wafers to record the location of the rejects on the wafer. Depending upon their performance, the integrated circuit chips can be sorted for disposal, if rejected, or for specified uses and applications appropriate to the design and performance criteria they meet.
There are numerous wafer chucks of various configurations that are known for use in wafer level burn-in testing. For example, U.S. Pat. No. 6,910,254 to Wood et al. discloses a wafer chuck consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer and the second half establishes electrical communication between the wafer and the electrical test equipment. U.S. Pat. No. 5,929,651 to Leas et al. discloses an apparatus and method for simultaneously testing or burning in integrated circuit chips on a wafer. This apparatus comprises a glass ceramic carrier having test chips and means for connection to paths of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips with at least one voltage regulator for each product chip. The test chips can provide test functions such as test patterns and registers for storing test results.
U.S. Pat. No. 4,531,146 to Cutchaw discloses an apparatus for cooling a high-density integrated circuit package. The apparatus includes a base in which the circuit package or wafer is mounted and a heat exchanger which mounts on the base to enclose the wafer and carry away the heat generated during testing by means of a fluid coolant which is passed through the heat exchanger. The heat exchanger includes a housing having a cooling chamber, one surface of which is formed of a pliable thin wall diaphragm of thermally conductive material. Heat generated by burn-in testing of the integrated circuits is exchanged across the diaphragm of thermally conductive material. A liquid coolant is passed through the chamber of the heat exchanger under pressure but does not come into direct contact with the device under test.
U.S. Pat. No. 6,108,937 to Raaijmakers discloses apparatus and method for cooling semiconductor wafers. In one embodiment a wafer and its supporting structure is lifted after high temperature testing to a position in close proximity to a cold wall of a thermal processing chamber which acts as a heat sink. Conductive heat transfer across a small gap from the wafer to the heat sink facilitates the cooling of the wafer. Other embodiments are disclosed but generally involve the concept of bringing the heated wafer under test into close proximity with a cooling station or plate to accomplish the heat transfer and cooling of the wafer.
U.S. Pat. No. 5,168,348 to Chu et al. discloses a heat transfer mechanism for removing heat generated in electronic circuit modules. Chu et al. utilize an impingement cooled compliant heat sink to extract heat from an array of computer chips in an electric module. Though various embodiments are disclosed, the most basic utilizes a metal sheet brought into contact with chips or a multi-chip module with the metal sheet acting as a spreader plate for jet impingement immersion cooling with fluorocarbon, liquid nitrogen or other dielectric liquids.
Known methods and apparatus for testing of integrated circuits generally rely upon an element in the testing apparatus that acts as a heat sink or heat exchanger to receive heat from the wafer under test after the wafer has been run through a test cycle. Further, known apparatus generally are not utilized to regulate the temperature of the wafer under test or t

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