Wafer-level burn-in and test

Details Wafer-level burn-in and test Wafer-level burn-in and test

2000-05-16

2003-02-25

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754090, C324S760020

Reexamination Certificate

active

06525555

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to exercising semiconductor devices and, more particularly, to performing test and burn-in on semiconductor devices to identify known good die (KGD) and, more specifically, to exercising semiconductor devices at wafer-level (prior to their being singulated, or “diced”, from the wafer).
BACKGROUND OF THE INVENTION
Semiconductor devices, from microprocessors to memory chips, are fabricated by performing a long series of process steps such as etching, masking, depositing and the like on a silicon wafer. A typical silicon wafer is in the form of a six inch diameter disc, or larger. Many semiconductor devices, typically identical to one another, are fabricated on a single silicon wafer by placing them in a regular rectangular array. Kerf lines (scribe streets) are disposed between adjacent semiconductor devices on the wafer. Ultimately, the devices are singulated from the wafer by sawing along the scribe streets.
Due to defects in the wafer, or to defects in one or more of the processing steps, certain ones of the semiconductor devices will not function as designed, these defects may show up initially or may not be apparent until the device has been in operation for an extended period of time. Thus it is important to test and electrically exercise the devices for an extended period of time to ascertain which devices are good and which are not good.
Typically, semiconductor devices are exercised (burned-in and tested) only after they have been singulated (separated) from the wafer and have gone through another long series of “back-end” process steps in which they are assembled into their final “packaged” form.
From a “global” perspective, a typical “back-end” process flow of the prior art is as follows (commencing with wafer fab)
Wafer Sort #
1
;
Laser Repair;
Wafer Sort #
2
;
Wafer Saw;
Package Assembly steps, such as die attach, wire bond, encapsulation, lead trim and form, lead plating;
Electrical Test;
Burn-In;
Electrical Test; and
Mark and Ship product.
Modern semiconductor devices often contain hundreds of terminals (i.e., “pads” such as power, ground, input/output, etc.) and modern semiconductor wafers often contain hundreds of semiconductor devices, resulting in each wafer having tens of thousands of pads, or test points, which need to be accessed in order to carry out testing and/or burn-in at wafer-level (i.e., testing all the dice at one time) prior to singulating the dice from the wafer. Precise alignment is also a non-trivial issue, when dealing with spacings (pitch) between adjacent pads as close as 4 mils. Nevertheless, performing testing and/or burn-in on semiconductor devices, prior to their being singulated from the wafer has been the object of prolonged endeavor.
U.S. Pat. No. 5,570,032 (Atkins, et al.; “Micron Patent”; October 1996) discloses wafer scale burn-in apparatus and process wherein a wafer (
14
) being burned-in is mated to a printed circuit board (
13
) which electrically contacts the pads on each die on the wafer using small conductive pillars (
15
) on the printed circuit board. Precise alignment of the entire wafer with the printed circuit board is required in order to permit testing all the dice on the wafer in parallel, eliminating the need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test.
FIG. 1
of the Micron Patent provides a general overview of the prior art processing steps in taking a wafer from fabrication to shipment.
FIG. 8
of the Micron Patent provides a comparable overview of the processing steps in taking a wafer from fabrication to shipment when utilizing the disclosed method of wafer scale burn-in and testing. It is suggested in the Micron Patent that it is also possible to have a printed circuit board with reduced connections and controlling logic (microprocessors, multiplexers, etc.), and to have complete test electronics included in the printed circuit board (see column 5, lines 53-60).
U.S. Pat. No. 5,532,610 (Tsujide, et al.; “NEC Patent”; July 1996) discloses apparatus for testing semiconductor wafer wherein there is a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on a wafer to be tested, and a plurality of pads disposed on a front surface of the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer. The testing substrate (
2
) may be a wafer, made of the same material as the wafer (
1
) so be tested. On the testing substrate (wafer)
2
, lead lines
7
extend from pads
4
and are connected to a power supply, a ground line
8
, an I/O line
9
, and a chip selecting line
10
.
FIG. 4
of the NEC PATENT illustrates a testing apparatus
16
made of a silicon wafer, the back surface of which has been etched to have apertures
21
of a quadrangular pyramid shape which can serve as alignment marks to thereby make it easy to register the testing substrate (
16
) with the wafer (
17
) to be tested.
U.S. Pat. No. 5,434,513 (Fujii, et al.; “Rohm Patent”; July 1995) discloses semiconductor wafer testing apparatus using intermediate semiconductor wafer wherein bump electrodes are formed on the bottom surface of an intermediate semiconductor wafer employed as a test substrate, and pickup electrodes and control electrodes are formed on the top (opposite) surface of the test substrate. A switching circuit is formed in the intermediate semiconductor wafer, and serves to connect selected ones of the bump electrodes to the pickup electrodes in accordance with switching control signals provided from a tester via the control electrodes. The pickup electrodes and the control electrodes are connected to the tester via pogo pins.
U.S. Pat. No. 5,497,079 (Yamada, et al.; “Matsushita Patent”; March 1996) discloses semiconductor testing apparatus, semiconductor testing circuit chip, and probe card wherein a plurality of semiconductor testing chips (
2
) are mounted to a one side of a motherboard (
4
) and a like plurality of on item of semiconductor integrated circuit chips (
1
) to be tested are mounted to an opposite side of the motherboard (
4
). A computer (
3
) is provided for controlling the semiconductor testing chips (
2
). Since the major testing functions are incorporated into the testing circuit chips (
2
), the computer (
3
) for collecting the test results can be a low-price computer.
FIGS. 5
,
7
and
10
of the Matsushita Patent illustrates a representative semiconductor test circuit chip (
2
) having test pattern generating means, a driver for applying the test pattern to the devices being tested, data storing means, data judging means for judging whether stored output data indicates a failure or not, and means for transferring a judgment result to a work station.
FIG. 12
of the Matsushita Patent illustrates the structure of a semiconductor testing apparatus used in a wafer test wherein a plurality of semiconductor testing chips (
2
) are mounted to a probe card (
103
), a plurality of probe needles (
104
) extending from the probe card (presumably from the opposite surface of the probe card), and a wafer (
106
) being tested. When a control signal is transmitted from the work station to the semiconductor testing circuit chips, the semiconductor testing chips start testing the semiconductor integrated circuits formed on the semiconductor wafer.
Generally, previous attempts at implementing schemes for wafer-level testing have involved providing a single test substrate with a plurality of contact elements for contacting corresponding pads on the wafer being tested. As mentioned hereinabove, this may require many tens of thousands of such contact elements and extremely complex interconnection substrates. As an example, an 8″ wafer may contain 500 16 Mb DRAMs, e

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