Wafer-level burn-in and test

Details Wafer-level burn-in and test Wafer-level burn-in and test

1997-01-15

2000-05-16

Brown, Glenn W.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324757, 324760, 324762, G01R 1073, G01R 3126

Patent

active

060642130

ABSTRACT:
Wafer-level burn-in and test of semiconductor devices under test (DUTs) includes a test substrate having active electronic components (e.g. ASICs) secured to an interconnection substrate, spring contact elements effecting interconnections between the ASICs and the DUTs. This is advantageously performed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs. The spring contact elements may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller.

REFERENCES:
patent: 3827820 (1974-08-01), Hoffman
patent: 5172050 (1992-12-01), Swapp
patent: 5261155 (1993-11-01), Angulas et al.
patent: 5363038 (1994-11-01), Love
patent: 5367254 (1994-11-01), Faure et al.
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5686842 (1997-11-01), Lee
patent: 5764072 (1998-06-01), Kister

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