Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-07-19
2002-01-08
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C361S761000
Reexamination Certificate
active
06337576
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to functional testing of integrated circuit to determine operational reliability. More particularly, the present invention is directed to a system and method of wafer-level functional testing of integrated circuits
Reliability testing is employed to identify integrated circuits with undesirably short operational lives. It is well known that the greatest quantity of operational failures occurs within a few hours of operational testing. To identify integrated circuits with short operational lives, test signal patterns are applied to the integrated circuits to repeatedly stimulate all devices and wires in the circuit. Traditionally, the integrated circuits are mounted into single or multiple chip packages and may be mounted to an additional substrate, such as a printed circuit board. This is accomplished by segmenting the wafer in which the circuits are formed into individual chips or dies, i.e., the integrated circuits are diced from the wafer. The test signals are then applied to the integrated circuits via leads in the package or signal traces on the printed circuit board. To decrease the time required to test the circuits, testing is performed at elevated operational temperatures, referred to as burn-in testing. The elevated temperatures accelerate inchoate failures.
Nonetheless, burn-in testing has historically been time-consuming, leading to reduced integrated circuit throughput and increased costs of manufacturing reliable integrated circuits. One technique advanced to increase integrated circuit throughput employs printed circuits boards having multiple sockets adapted to receive and electrically couple the circuit to a source of test signals. This allows simultaneously testing a great quality of integrated circuits. With this process, however, the probability of processing bad or unreliable circuits before detecting defects is great.
Another burn-in technique for improving throughput is referred to as wafer level burn-in. The wafer level burn-in test involves testing whole, or parts of whole, wafers containing integrated circuits before segmenting the integrated circuits from the wafer. To that end, the wafer is manufactured with test points and a test apparatus is formed to contact the test points allowing test signals to propagate from a signal source through the test apparatus and onto the integrated circuits. The test points may be formed onto the integrated circuit itself, or disposed remotely with respect thereto to minimize the damage to the integrated circuit by the test apparatus. A drawback with prior art wafer level burn-in concerns mismatch between the coefficients of thermal expansion of the test apparatus and the wafer during burn-in, as well as the adverse effects of a defective test apparatus during burn-in. For example, it is often difficult to determine whether an integrated circuit identified as being defective is a result of a defect in the integrated circuit or a defective test apparatus, resulting in a entire wafer of operational integrated circuits being improperly discarded. In addition, a defective test apparatus can result in catastrophic failure rendering the entire wafer defective.
What is needed, therefore, is a burn-in testing technique that facilitates identifying defects attributable to a test apparatus from defects attributable to an integrated circuit, while avoiding the problems associated with catastrophic failures of a test apparatus.
SUMMARY OF THE INVENTION
A method and a system for wafer level burn-in testing of a circuit features flip-jumper to permit selectively connecting signals to the interconnect sites on the wafer that are in constant electrical communication with a region of the wafer. The method includes forming a plurality of interconnect sites, with a first subset of the interconnect sites are in constant signal communication with the region. The region may comprise of a circuit integrally formed with the wafer or an area of the wafer having bond sites to which a circuit may be mounted, thereby placing the circuit in constant communication with the first subset A second subset of the interconnect sites are selectively placed in data communication with the circuit by selectively placing the first and second subsets in signal communication. Signals are transmitted between the circuit and the signal source, with the signals selected from the group consisting of DC or AC signals. Specifically, the signal source is placed in data communication with one or more burn-in driver connections formed on the wafer to be in constant electrical communication with the second subset. The signal source is placed in electrical communication with the driver connections. Typically, the first and second subsets include multiple interconnect sites. The burn-in driver connections may be formed in a region of the wafer so as to bifurcate the same. However, to make efficient use of the surface area of the wafer, the driver connections may be formed on the periphery of the wafer, thereby being disposed radially symmetrically about the circuit.
Preferably, a plurality of circuits are formed on the semiconductor wafer and the interconnect sites are arranged in multiple sets. Each of the multiple sets is associated with one or more of the plurality of circuits and includes the first and second subsets. Typically, the circuits associated with one of the multiple sets differ from the circuits associated with the remaining sets of the multiple sets.
Selective communication between the first and second subsets is achieved by the flip-jumper. To that end, the flip-jumper includes connection pads configured to connect with the second subsets. In this manner, the flip-jumper places the signal source in data communication with the circuit by selectively placing the first and second subsets in signal communication. The flip-jumper may be formed from virtually any material suitable for substrate manufacture, including printed circuit board material or semiconductor material. One or more electronic elements are disposed between pairs of the connection pads. The electronic elements are connected in series between one of the interconnects of the first subset and one of the interconnects of the second subset upon the flip-jumper reaching a final seating position with respect to the semiconductor wafer. The electronic elements are selected from the group consisting of a wire, fuse, a resistor, a capacitor and a transistor. Although the flip-jumper may connect to all of the interconnect sites on the wafer, it is preferred that the flip-jumper connect with segments of the plurality of interconnect sites. In this fashion, multiple flip-jumpers may be employed to connect the plurality of circuits to the signal source. This permits segmenting the wafer into various test areas which increases the operational reliability of the wafer during burn-in testing.
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Avery George E.
Brown Sammy K.
Calamoneri Allan
Goetz Martin P.
Wiggin Andrew K.
Alpine Microsystems, Inc.
Brooks Kenneth C.
Kerveros J
Metjahic Safet
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