Metal working – Means to assemble or disassemble – With means to test work or product
Reexamination Certificate
2000-03-11
2003-05-06
Eley, Timothy V. (Department: 3724)
Metal working
Means to assemble or disassemble
With means to test work or product
C029S593000, C029S407010, C029S03400A, C029S564100, C029S650000
Reexamination Certificate
active
06557244
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of wafer level packaging and testing, and more specifically to a wafer level board/card assembly process.
BACKGROUND OF THE INVENTION
The advance of semiconductor technology in recent years has greatly increased the density of a semiconductor device. In order to satisfy the strong market demand of highly portable and compact electronic gadgets, many semiconductor manufacturers are dedicated to the fabrication of integrated circuits with densely populated semiconductor devices, a large number of input/output (I/O) terminals and fast processing speed. After the fabrication of integrated circuits on a wafer, each die on the wafer needs to be properly tested and packaged to prevent it from being damaged by moisture or external forces.
As the number of I/O pins and the processing speed of a circuit device-increase, the technology of packaging the die becomes more and more critical. How to package a large number of pins in a small volume and maintain the high processing speed of the device have to be carefully considered. In addition, the issue of heat dissipation from the high density circuit must be addressed. After each die is packaged, the circuit on the die has to be tested to ensure that it functions properly as designed.
In general, the conventional wafer testing procedure includes primarily first wafer sorting, laser repairing, second wafer sorting and burn-in. The first three steps are performed in the wafer level. The step of burn-in is performed after the wafer is sawed and each die has been cut off from the wafer, sealed and packaged as an individual integrated circuit.
The first wafer sorting is to test if there are problems in the wafer fabrication process that result in malfunction of the integrated circuit in a die. The step of laser repairing is usually used to repair the defective storage units in memory devices such as DRAM or SRAM. After the laser repairing, the second wafer sorting is used to examine if the repairing has been accomplished successfully. The repaired dice are tested to determine if they function properly as designed. In generally, only one or two wafers from a cassette of 25 or 50 wafers are sampled and tested.
In the conventional packaging technology, each individual die sealed and assembled as an integrated circuit in a package such as TSOP, SOJ, QFP and BGA, . . . , etc. is under burn-in on a test socket separately. Different test sockets are required for testing the devices that have different types of packages. The purpose of the burn-in process is to identify and remove the devices that suffer from infant mortality.
The conventional burn-in technology relies on a burn-in system that sends signals to directly control the integrated circuit. During a test cycle, 50% of the duty cycle is used and only one address bit can be controlled. Most of the tests use write cycle only. Therefore, the burn-in process may take several hours to several days to complete. Because of the inefficiency, a packaged integrated circuit spends a long time on a burn-in board that sometimes causes the pins of the circuit to be bent and damaged. Both the burn-in boards and burn-in sockets do not last very long.
As a result, the cost associated with the burn-in step is high. In addition, if the burn-in step detects defects caused by a wafer process problem, the problem is uncovered only after many integrated circuits have been packaged and many wafers have been fabricated. Therefore, there is a strong demand in having a better wafer packaging, testing and assembly process that can uncover the defects and reflect the wafer process problem as early as possible to reduce the cost and improve the yield of manufacturing integrated circuits.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the above-mentioned drawbacks of conventional wafer packaging and testing techniques. The primary object of the invention is to combine semiconductor chip packaging, testing and assembly into an integrated process performed at wafer level. The integrated wafer level process reduces the frequency of loading and unloading wafers and increases the throughput of manufacturing the semiconductor chips.
Another object of the invention is to provide an automatic in-line process for wafer level board/card assembly. According to this invention, the automatic wafer level board/card assembly process comprises first wafer sorting, laser repairing, second wafer sorting, wafer level burn-in, wafer level packaging, final testing, wafer sawing, and board/card assembly. The output data such as wafer mapping and yield data of each process step are sent to a computer server and used as the input data to the next process step.
It is also an object of the invention to provide a wafer level burn-in method for the integrated assembly process. A burn-in circuit and a plurality of internal probing pads are built in the circuit of the integrated circuit chip manufactured by the process of this invention. By using a prober and a probe card, appropriate voltages and control signals can be provided to the integrated circuit of each die at wafer level to put the circuit device under burn-in. Multiple dice can be under burn-in at the same time. The burn-in time is reduced from several days to several seconds.
It is yet another object of the invention to provide a board/card assembly process for the final assembly of a PC board and integrated chips. According to the invention, the dice are packaged on the wafer. After the wafer level packaging, the wafer is sawed to separate the packaged integrated chips. A multi-chip module die bonder, an IR re-flow machine and an open/short tester are used to assemble, test and sort the board/card to produce the chip product.
In the present invention, many of the process steps are performed with a tester and a prober. Wafers are transported from one step to a next step in a wafer cassette. Automatic wafer loading, wafer alignment and wafer unloading are provided by the existing prober. The wafer mapping, bin/yield data and repairing data of each process step can be sent to the computer server by the tester/prober. The computer server can also load testing programs and setup the tester.
Accordingly, it is yet an object of the invention to provide an automatic integrated in-line process system connected to the world wide internet. The output information at each process step can be transmitted to a client in real time. Test results from wafer sorting or testing can be used to uncover wafer process problem early and improve the yield of manufacturing the wafer and the integrated circuit chips.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from a careful reading of a detailed description provided herein below, with appropriate reference to the accompanying drawings.
REFERENCES:
patent: 4654964 (1987-04-01), Schneider et al.
patent: 5640762 (1997-06-01), Farnworth et al.
patent: 6008636 (1999-12-01), Miller et al.
patent: 6148511 (2000-11-01), Taguchi
patent: 6158119 (2000-12-01), Crist et al.
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