Wafer level assembly package

Details Wafer level assembly package Wafer level assembly package

2006-07-04

2006-07-04

Owens, Douglas W (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Reexamination Certificate

active

07071544

ABSTRACT:
A wafer level package mainly comprises a semiconductor wafer and a plurality of bonding pads disposed on the active surface of the wafer. It is characterized in that there is a protection layer formed on the back surface of the wafer, wherein the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the bonding pads. In such a manner, the protection layer will prevent the back surface of the wafer from being contaminated with the solder material. Moreover, when a UBM layer is further provided on the bonding pad, the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the UBM layer.

REFERENCES:
patent: 6326698 (2001-12-01), Akram
patent: 6787903 (2004-09-01), Yang
patent: 506050 (1989-11-01), None

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