Wafer-level antenna effect detection pattern for VLSI

Details Wafer-level antenna effect detection pattern for VLSI Wafer-level antenna effect detection pattern for VLSI

1999-12-20

2002-04-16

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

With measuring or testing

C257S048000, C257S053000, C257S428000, C257S429000, C438S017000

Reexamination Certificate

active

06372525

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to testing and diagnostics of line processes used for the manufacture of integrated circuit devices and more particularly to the measurement and monitoring of plasma damage from back-end-of-line processes.
(2) Description of Prior Art
The manufacture of large scale integrated circuits in a mass production facility involves hundreds of discrete processing steps beginning with the introduction of blank semiconductor wafers at one end and recovering the completed chips at the other. The manufacturing process is usually conceived as consisting of the segment wherein the semiconductor devices are formed within the silicon surface(front-end-of-line) and the portion which includes the formation of the various layers of interconnection metallurgy above the silicon surface(back-end-of-line). Most of these processing steps involve depositing layers of material, patterning them by photolithographic techniques, and etching away the unwanted portions. The materials consist primarily of insulators and metal alloys. In some instances the patterned layers serve as temporary protective masks. In others they are the functional components of the integrated circuit chip.
Radio-frequency(rf) plasmas are used extensively in many of these processing steps, in particularly for back-end-of-line. Their usefulness stems from the fact that they are dry processes and they provide the cleanliness and the dimensional and compositional control required in integrated circuit manufacture. Plasma etching processes, in particular Reactive-ion-etching (RIE) permit a high degree of pattern definition and precise dimensional control. RIE combines gaseous chemical etching with unidirectional ion bombardment provided by an rf plasma. Plasma etching, is accomplished at higher pressures, is isotropic although some forms of plasma etching also provide anisotropic etching. Photoresist layers are frequently removed, not by chemical solvents, but more cleanly by plasma aching.
The unfortunate consequences of these numerous exposures of semiconductor wafers to rf plasmas and other forms of ionic radiation, is the occurrence of radiation damage and the accumulation of charge on exposed conductive components which leads to damaging current flows and trapped charge affecting the semiconductor devices.
The most important semiconductor device in current technology is the metal-oxide-silicon-field-effect-transistor (MOSFET). It is a simple device consisting of two shallow regions of one type semiconductor—the source and the drain—separated by a region of another type. The conductivity of the central region(channel) is modulated by applying a voltage to an electrode(gate) which overlies the channel region and is separated from it by a thin insulating layer (gate oxide). CMOS (complementary MOS) technology utilizes MOSFETS in pairs, one an n-type channel device (NMOS) and the other a p-type channel device (PMOS). The simple nature of these devices and their minimal heat dissipation permits an extraordinary degree of miniaturization and consequently a high density of circuits. The gate electrode is no longer made of metal but of heavily doped polysilicon. In the late 1980s the design rule for these devices was 3.5 microns. Today's design rules are approaching 0.18 microns.
The gate insulating layer which overlies the channel region usually consists of thermally grown silicon oxide and is one of the most critical components of the MOSFET. For the 3.5 micron technology this silicon oxide layer is about 600 Angstroms thick. The gate oxide used in 0.25 micron design technology is of the order of only 50 Angstroms. High performance logic devices having gate oxides as thin as 30 Angstroms are reported for 0.18 micron design rules. An insulating film of these dimensions it highly susceptible to damage from external sources during manufacture. A prominent cause of such damage is ion and electron bombardment from plasmas used in the back-end-of-line processing. The surfaces of patterned semiconductor wafers located within a plasma reactor present multiple areas of conductors and insulators to the plasma. These produce local non-uniformities in the plasma currents which result in charge build-up on the electrically floating conductor surfaces.
After the gate oxide layer is formed it is covered with a layer of polysilicon within which the gate electrode is defined. The etching of this polysilicon layer is accomplished by reactive-ion-etching, providing the first in a series of exposures of the gate oxide to an rf plasma. In this instance the area of the gate electrode is covered with photoresist. As etching proceeds the exposed polysilicon provides sufficient conduction to prevent local charge build-up. However, as the endpoint is approached, the polysilicon layer breaks up and residual, now isolated, regions of polysilicon surrounding the photoresist protected gate electrode act as an antenna which accumulate positive charge. This results in the development of a positive potential sufficiently high to cause current flow through the gate oxide. These polysilicon halos can present a high antenna-to-thin oxide area ratio causing massive current flow in the oxide. As etching proceeds, the halos of polysilicon disappear and the antenna area is reduced to the thin edges of the gate electrode itself.
Subsequent sundry processing steps provide multiple exposures of the gate oxide to damage by plasmas and ionizing radiation. The nature of the exposure and the avenues available for reducing it are different and are unique to each processing step.
The mechanism of current flow though a gate oxide is primarily Fowler-Nordheim(FN) tunneling. (FN) tunneling which occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 Angstroms. Such potentials are easily achieved in conventional plasma reactors. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide and subsequent dielectric breakdown.
The multiple exposures of the gate oxide to steps involving plasmas has led to the emergence of several test structures designed to amplify the charging exposure and thereby allow proper and timely assessment of the damage delivered by the sundry plasma processing steps (See Wolf, S.,
Silicon Processing for the VLSI Era
, Vol3, Lattice Press, Sunset Beach, Calif., Vol.3 (1995),p507-9). These test structures fall into two types: 1) Antenna structures which have large areas of conductor exposed to the plasma as compared to the area of the gate oxide; and 2) large area capacitors which are formed over the gate oxide.
Nariani, et. al., U.S. Pat. No. 5,638,006 shows an antenna structure which is designed to draw charge to a region of thin oxide of an MOS device thereby exaggerating the exposure to damage. Similar antenna structures having charge accumulating pads of various antenna ratios are patterned on successive metallization levels are widely used. Bui, U.S. Pat. No. 5,650,651 shows the use of an auxiliary capacitor which reduces the antenna ratio of a pad on the uppermost layer of metallization of a carrier injection test transistor. The capacitor is formed over thin oxide in a separate region and draws away tunneling current from the test transistor. A Faraday cage type shielded structure for assessing plasma damage is shown by Shiue, et. al., U.S. Pat. No. 5,781,445. A conductive cage shields a reference MOSFET from plasma radiation during a plasma processing step. Comparison of threshold voltage shifts is made between the shielded and unshielded devices after a selected plasma process step and the plasma damage incurred by the unshielded devices is calculated.
These test structures indicate the presence or absence of radiation damage but are not able to adequately pinpoint the processing steps responsible for the damage. In addition they frequently produce ambiguous results because their st

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