Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-08-27
2002-12-24
Niebling, John F. (Department: 2812)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C438S014000
Reexamination Certificate
active
06498504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer inspection device and a wafer inspection method to be used for inspection of an integrated circuit mounted on a wafer, more particularly, a wafer inspection device and a wafer inspection method in which measuring efficiency is improved.
2. Description of the Related Art
Recently, to manufacture a semiconductor device, a process of inspection of operation of integrated circuits (ICs) formed on an Si wafer exists.
FIG. 1A
is a schematic view showing the arrangement of the ICs formed on an Si wafer, and
FIG. 1B
is a schematic view showing the positions of electrode pads provided on four ICs.
Generally, in a typical memory product, approximately 500 ICs are formed on an 8-inch wafer, however, for convenience, 108 ICs are shown in FIG.
1
A. Also, approximately 60 electrode pads are provided on one IC, however, only 12 electrode pads
402
are shown in FIG.
1
B.
Conventionally, on such a wafer
401
, for example, 4 probes are arranged each horizontally and vertically, and 16 probe cards for measurement are used to output a test pattern from a test head to the ICs via a test board, and the results are detected by the test head, whereby the ICs are inspected one by one.
However, in such an inspection method, the probes are arranged horizontally and vertically in a square or rectangular matrix form, however, the ICs are closely provided as much as possible within the disk-shaped wafer
401
and arranged so as to be along the outer circumference of the wafer. Therefore, when ICs formed on one wafer
401
are inspected, all probes in the matrix arrangement cannot be contacted with the ICs. For example, in
FIG. 1A
, the probes come into contact with only the arrangement of indexes 1, 7, 8, 15, 16, 17, 25, 26, 27, and 28 of ICs, that is, the matrix of 16 probes comes into contact with 10 ICs, so that probes at positions where ICs do not exist are not used and remain unused. Such a loss frequently occurs at the outer circumferential portions of the wafer, so that a great loss occurs in the wafer measuring time, and reduction in the measuring time has been demanded.
Therefore, a device and a method by which all ICs formed on one wafer are collectively inspected have been disclosed (Japanese Unexamined Patent Publication No. H10-223704).
FIG. 2
is a schematic sectional view showing the conventional collective inspection device disclosed in Japanese Unexamined Patent Publication No. H10-223704.
FIG. 3A
is a sectional view showing the peripheral portion of projecting terminal
306
of
FIG. 2
, and
FIG. 3B
is a sectional view showing the peripheral portion of O-ring
325
of FIG.
2
.
In this conventional collective inspection device, a chamber
300
into which a wafer
302
to be inspected is sealed and an arm
301
for conveying the wafer
302
into the chamber
300
are provided. In addition, a gate valve
304
is provided at the gateway of the arm
301
of the chamber
300
, and gas a supply port
310
and a gas exhaust port
311
are provided at the upper part of the chamber
300
.
Furthermore, at a lower part of the chamber
300
, a ring-shaped position adjusting mechanism
305
is provided. An O-ring
325
is attached onto the position adjusting mechanism
305
, and at the side more inner than the O-ring, a transparent contactor
307
is provided. As shown in
FIG. 3A
, projecting terminals
306
equal in number to the electrode pads
331
formed on the wafer
302
are formed on the upper surface of the contactor
307
. On the other hand, connection terminals (not shown) equal in number to the projecting terminals
306
are formed on the lower surface of the contactor
307
.
As shown in
FIG. 3B
, an exhaust passage making communication between the inside and the outside of the O-ring
325
is formed immediately under the O-ring
325
of the position adjusting mechanism
305
, and is connected to tube
326
outside the O-ring
325
. The tube
326
is connected to a vacuum pump (not shown) provided outside the chamber
300
via the exhaust passage formed in the chamber
300
.
Furthermore, a test head
318
is disposed below the chamber
300
, and on the test head
318
, a connection ring
303
is connected via pogo pins
320
. Connection terminals (not shown) equal in number to the connection terminals formed at the contactor
307
are formed on the upper part of the connection ring
303
, however, the number of pogo pins
320
is approximately one tenth of the number of the connection terminals. Furthermore, a multiplexer (not shown) is installed inside the connection ring
303
, and by this multiplexer, connection terminals from which signals inputted into the pogo pins
320
are outputted are switched.
In the conventional collective inspection device thus constructed, the wafer
302
is vacuum-adsorbed by the arm
301
and conveyed into the chamber
300
. Then, when the center of the wafer
302
and the center of the contactor
307
almost coincide with each other in plane view, the arm
301
lowers until the wafer
302
comes into contact with the O-ring
325
. When the wafer
302
comes into contact with the O-ring
325
, the gate valve
304
is closed. Thereafter, heating or cooling gas is supplied from the gas supply port
310
into the chamber
300
, and unnecessary gases are exhausted from the gas exhaust port
311
. When the temperature inside the chamber
300
reaches a desired temperature, XY coordinates of the projecting terminal
306
and the electrode pad
331
are read through the transparent contactor
307
by an alignment mechanism (not shown), and based on this read data, the position of the contactor
307
is finely adjusted so as to coincide with the projecting terminal
306
by the position adjusting mechanism
305
. After completing alignment, the space surrounded by the O-ring
325
via the exhaust passage and the like provided at the position adjusting mechanism
305
and chamber
300
is decompressed. Thereby, the O-ring
325
is collapsed, and the projecting terminal
306
comes into contact with the electrode pad
331
. Thereafter, the chamber
300
is lowered, and the connection terminals formed on the lower surface of the contactor
307
and the connection terminals provided on the connection ring
303
are connected to each other.
Then, a test pattern is outputted from the test head
318
to the connection ring
303
, is inputted into all electrode pads
331
of the wafer
302
from the predetermined connection terminals in order via the multiplexer, whereby inspection of each IC is conducted.
After completing the inspection, the chamber
300
rises to disconnect the connection terminals of the contactor
307
and the connection terminals of the connection ring
303
, and then, the gate valve
304
is opened and the wafer
302
is carried out from the chamber
300
by the arm
301
.
By such a conventional collective inspection device, theoretically, only switchover of signal lines by the multiplexer makes it possible to inspect all ICs.
However, the concrete construction of the multiplexer is not disclosed in the abovementioned patent publication, and at present, it is considered that production of the abovementioned multiplexers for thirty thousands electrode pads cannot be realized. Therefore, theoretically, inspection efficiency is improved by using the device disclosed in Japanese Unexamined Patent Publication No. H10-223704, however, in actuality, the problem of low inspection efficiency still remains, and the problem that unused contact pins exist also remains.
SUMMARY OF THE INVENTION
The object of the invention is to provide a wafer inspection device and a wafer inspection method by which inspection efficiency can be improved.
A wafer inspection device according to the present invention conducts inspection of a plurality of integrated circuits provided with a plurality of electrode pads respectively. The wafer inspection device comprises: a test head which outputs a test pattern from a plurality of tester pogo pins; a test board to which the te
NEC Corporation
Niebling John F.
Stevenson Andre′ C
Young & Thompson
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