Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2000-03-29
2004-04-20
Johns, Andrew W. (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C382S147000, C382S149000
Reexamination Certificate
active
06724929
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer inspecting apparatus for classifying kinds of defects on a face to be inspected of a wafer formed with a circuit pattern by using, for example, a CAD (Computer Aided Design) apparatus.
2. Description of the Related Art
FIG. 2
is an outline constitution diagram showing an example of a conventional wafer inspecting apparatus.
The wafer inspecting apparatus is provided with a patterned wafer defect inspecting unit
1
. The patterned wafer defect inspecting unit
1
is provided with a function of sampling for respective chips an image of a face to be inspected of a wafer formed with a circuit pattern based on wiring information of a circuit for the respective chips and forming and outputting coordinate value data S
1
representing positions and sizes of defects present on the face to be inspected for the respective chips. A wafer map display unit
2
is connected to an output side of the patterned wafer defect inspecting unit
1
. The wafer map display unit
2
inputs the coordinate value data S
1
and displays the positions and the sizes of the defects present on the face to be inspected of the respective chips by using a wafer map.
According to the wafer inspecting apparatus, a wafer constituting an object of inspection is inspected by the wafer defect inspecting unit
1
and the coordinate value data S
1
is output by the wafer defect inspecting unit
1
. The coordinate value data S
1
is input to the wafer map display unit
2
and a wafer map in correspondence with the coordinate value data S
1
is displayed by the wafer map display unit
2
.
FIG. 3
is a schematic diagram showing an example of a display screen of the wafer map display unit
2
in FIG.
2
.
According to the display screen, a number of defects is displayed by a numeral at a corresponding location and a shape of a defect is displayed by, for example, a mark. Further, according to the wafer inspecting apparatus, there is carried out a defect control concerning a defect distribution, a number of defects and sizes of defects in the wafer map of
FIG. 3
by optical observation of an operator and a defect analysis is carried out using a sampling method.
However, according to the conventional wafer inspecting apparatus of
FIG. 2
, there are the following problems itemized as (i) and (ii).
(i) According to the wafer inspecting apparatus of
FIG. 2
, only defects are displayed on the display screen and a defect analysis taking into consideration a correlation between defects and a circuit pattern cannot be carried out.
(ii) According to the wafer inspecting apparatus of
FIG. 2
, the apparatus cannot express a correlation relationship between the circuit pattern and positions of defects as well as sizes of defects. Therefore, for example, when two patterns are shortcircuited, the apparatus cannot determine whether a serious defect is constituted.
SUMMARY OF THE INVENTION
In order to resolve the above-described problems, according to an aspect of the invention, there is provided a wafer inspecting apparatus comprising wafer inspecting means for acquiring for respective chips an image of a face to be inspected of a wafer formed with a circuit pattern based on wiring information of a circuit at the respective chips and forming and outputting coordinate value data representing positions and sizes of defects present on the face to be inspected for the respective chips, image data forming means for forming graphic figures representing the respective defects based on the respective coordinate value data for the respective chips and generating image data in correspondence with the graphic figures, analyzing means for inputting the image data, analyzing a state of overlapping of a first image in correspondence with the image data and a second image representing the circuit pattern based on the image information and outputting analyzed data, and classifying means for inputting the analyzed data and classifying a kind of the respective defect based on the analyzed data.
By adopting such a construction, the wafer is subjected to the wafer inspecting means, the image of the face to be inspected of the wafer is sampled for the respective chips and the coordinate value data representing the positions and the sizes of the defects is output by the wafer inspecting means. The coordinate value data is input to the image data forming means and the image data is output by the image data forming means. The image data is input to the analyzing means, the state of overlapping of the first image in correspondence with the image data and portions of the second image representing the circuit pattern in correspondence with the coordinate value data is analyzed and the analyzed data is output by the analyzing means. The analyzed data is input to the classifying means and the kind of the respective defect is classified by the classifying means.
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Adams & Wilks
Alavi Amir
Johns Andrew W.
Seiko Instruments Inc.
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