Wafer including test lead connected to ground for testing networ

Details Wafer including test lead connected to ground for testing networ Wafer including test lead connected to ground for testing networ

1981-01-16

1984-10-23

Strecker, Gerard R.

Electricity: measuring and testing

Plural, automatically sequential tests

324 51, 357 45, 361410, G01R 3102, G01R 3128, H01L 2700

Patent

active

044790880

ABSTRACT:
Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12', exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

REFERENCES:
patent: 3781683 (1973-12-01), Freed
patent: 3789205 (1974-01-01), James
patent: 3803483 (1974-04-01), McMahon
patent: 4183460 (1980-01-01), Yuen et al.
patent: 4220917 (1980-09-01), McMahon
patent: 4241307 (1980-12-01), Hong
patent: 4295182 (1981-10-01), Aubusson et al.
Collins, C. A., Logic Network Nodal Conductance IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3666-3668.
Klein et al., Chip Power Test Circuit IBM Tech. Discl. Bull., vol. 22, No. 8A, Jan. 1980, pp. 3256, 3257.
Greene et al., Photoconductor For Electrical Testing IMB Tech. Disclosure Bulletin, vol. 15, Aug. 1972, No. 3, pp. 904, 905.
Bove et al., Impedance Terminator For AC Testing Monolithic Chips IBM Tech. Disclosure Bull., vol. 15, No. 9, Feb. 1973, pp. 2681, 2682.

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