Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With thin active central semiconductor portion surrounded by...
Reexamination Certificate
2008-10-17
2010-06-15
Pham, Thanh V (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With thin active central semiconductor portion surrounded by...
C257SE21536, C438S694000
Reexamination Certificate
active
07737531
ABSTRACT:
A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.
REFERENCES:
patent: 6162702 (2000-12-01), Morcom et al.
patent: 7413501 (2008-08-01), Priewasser
patent: 2007/0141955 (2007-06-01), Masuda
patent: 2007/0231929 (2007-10-01), Kajiyama et al.
patent: 2008/0045015 (2008-02-01), Sekiya
patent: 2000-260670 (2000-09-01), None
Kobayashi Motoshige
Sugawara Yasuharu
Kabushiki Kaisha Toshiba
Munoz Andres
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Pham Thanh V
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