Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-21
2004-06-08
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06747464
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device electrical test systems, and more particularly to semiconductor device electrical test systems that allow for backside viewing of a semiconductor device while electrically probing its frontside.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A wafer fabrication process typically forms multiple identical integrated circuits upon and within frontside surfaces of each of several semiconductor wafers processed as a group (i.e., lot). Each individual integrated circuit is formed within a die area of one of the semiconductor wafers. Following wafer fabrication, the dice are subjected to “wafer sort” electrical testing, then separated from the wafers. Fully functional die are typically packaged and sold as individual semiconductor devices.
Wafer sort electrical testing is performed to ensure each integrated circuit functions properly according to a predetermined electrical specification. Following wafer fabrication, each wafer is typically placed, with the frontside surface of the dice facing up, upon a flat surface of a test system such as a wafer holder that can move in three-dimensions. A wafer under test is raised up by a translation stage until bonding pads of one of the integrated circuits contact fine probe needles of the test system. The test system may provide electrical power to the integrated circuit via some of the probe needles, and may provide input signals and/or receive output signals from the integrated circuit via other test probe needles. The wafer under test may be automatically lowered, repositioned, and raised again until all of the integrated circuits formed on the wafer under test have been tested via an automated probe station. A microscope may be mounted above the wafer surface to view the frontside surface of the wafer, where the microscope can be adapted for optical scanning of the die for photoemission-generating defects.
In recent years there has been an increase in the overall density of metal used in many integrated circuits near or at the frontside surface. This trend has led to the difficulty of optically detecting photoemission-generating defects of the dopant and thin-film areas that lie beneath the metal layers. Accordingly, it is difficult to scan the frontside surface of the individual die on the wafer. Flip-chip technology has compounded this problem. Flip-chip technology has become increasingly popular during the last few years, as the demand for more efficient and higher-density packaging of integrated circuits has markedly increased. The individual die, in the case of flip-chip technology, are manufactured to have the input/output (I/O) bonding pads of the die placed in a two-dimensional array across the frontside of the integrated chip as opposed to being placed on the perimeter of the die as found in conventional peripheral-terminal device dies. The flip-chip manufactured die in the process of being packaged is inverted (hence the term “flip-chip”) and the I/O pads of the die are solder-bump attached to a corresponding array of bonding pads on an upper surface of a packaging substrate. The packaging of flip-chip die save space on the packaging substrate, which allows for higher integrated circuit density packing, and the solder-bumps attachments allow for more efficient electrical coupling between the integrated circuits and the packaging substrate. However, the two-dimensional array of metal I/O pads on the frontside surface of the flip-chip die essentially precludes frontside viewing for photoemission-generating defects as done on existing conventional automated probe stations.
It is then desirable to provide a means for backside viewing of the wafer for optical scanning of photoemission-generating defects. A benefit would arise if such can be accomplished on existing frontside viewing and frontside probing automated probe stations. The desired backside viewing should be accomplished by inverting the wafer instead of inverting the microscope, because inverting the microscope would further require re-engineering of the existing frontside viewing automated probe stations to allow for an unobstructed view of the backside surface of the wafer.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by an improved integrated circuit test apparatus with a holder that is coupled to a three-dimensional translational mechanism. The holder is preferably adapted to receive a wafer that is inverted so that electrical probing can occur on the frontside of the wafer while the backside of the wafer can be concurrently viewed with an optical scanning mechanism configured above the test apparatus. According to one embodiment, the three-dimensional translational mechanism may be from a preexisting probe station, i.e., one that probes the frontside while viewing the frontside of the wafer. The integrated circuit test apparatus includes at least one electrically conducting probe needle for establishing electrical contact with the input/output (I/O) bonding pads of the individual die of the wafer undergoing testing. There may be as many as four or more probe needles used to make contact with the wafer. The three-dimensional translational mechanism allows for the movement of the holder in the x, y, and z directions for moving the wafer relative to the electrically conducting probe needles. In accordance with a specification of the layout of the dice on the wafer, the three-dimensional translational mechanism may be further configured to automatically step or reposition the wafer after probing an individual die to move to the next die in succession for automated multi-die probing of any select number of dice on the wafer.
The electrical conducting probe needles are each preferably attached to a probe base, where the probe base is configured to allow for the adjustment of the probe needles to align with I/O pads of a die to undergo probe testing. The probe base is in electrical communication with an external integrated circuit testing unit and power supply. In another embodiment, the probe needles may originate from a probe card. The optical scanning mechanism is adapted to detect photoemission-generated defects of the integrated circuits in the wafer by scanning the backside surface of the wafer that is undergoing frontside electrical probe testing. The optical scanning mechanism may include, among other things, a magnifying and focusing lens, an electromagnetic radiation beam source or electron beam source, and a microscope, where the microscope may be is a charged coupled device (CCD).
In addition to the testing apparatus discussed above, a method for testing an integrated circuit is contemplated herein. The method for testing an integrated circuit on a wafer may include holding the wafer in an inverted position with a holder. Electrically conducting probe needles are used to probe integrated circuits with I/O bonding pads on a frontside surface of the wafer and while optically scanning the backside surface of the wafer, and moving the wafer in the interim between each probing operation.
Moving the wafer in the interim between each probe operation is achieved by using a three-dimensional translational mechanism coupled to the holder, which allows the wafer that is retrofittedly attached to the holder to be moved in the x, y, and z directions. The three-dimensional translational mechanism may be configured in accordance with a specification of the layout of the die on the wafer, to incrementally step or automatically move from the last die tested to the next die on the wafer for any select number of die on the wafer.
Optically scanning the backside surface of the wafer is accomplished by an optical scanning mechanism, where the optical scanning mechanism may scan the backside of the wafer with a beam of electromagnetic radiation. The beam of electromagnetic radiation may be a beam of infrared radiation, since the backsides
Conley & Rose, P.C.
Nguyen Vinh P.
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