Wafer having a plurality of IC chips having different sizes form

Details Wafer having a plurality of IC chips having different sizes form Wafer having a plurality of IC chips having different sizes form

1998-03-12

1999-06-15

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

257 48, 257207, H01L 2102

Patent

active

059125020

ABSTRACT:
In a wafer having a plurality of integrated circuit chips of different chip sizes formed on the wafer, each of the integrated circuit chips having a number of externally connecting lands uniformly distributed over the whole surface of the chip with equal pitches to depict a matrix or a repeated pattern of an equilateral triangle, a plurality of power supply lands of the externally connecting lands are located to depict a cross having a crossing point positioned at a center of the chip. A geometrical location of the power supply lands is congruent to all said integrated circuit chips of different chip sizes. The pitch between adjacent lands positioning a dicing line therebetween is one obtained by multiplying the pitch between adjacent lands positioning no dicing line therebetween, by a positive integer.

REFERENCES:
patent: 5341024 (1994-08-01), Rosotker

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