Wafer having a dicing area having a step region covered with a c

Details Wafer having a dicing area having a step region covered with a c Wafer having a dicing area having a step region covered with a c

1990-08-17

1991-05-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437226, H01L 21304

Patent

active

050175122

ABSTRACT:
A conductive layer is formed at the step portion in a dicing line formed vertically and horizontally on a wafer and at a step portion of the region on which a test element for processing control formed inside of the dicing line or an alignment mark are formed, so as to completely cover the step portions. Since the conductive layer does not come off the step portions in subsequent steps, a short circuit of a wiring layer formed on a semiconductor chip region is prevented.

REFERENCES:
patent: 2970730 (1961-02-01), Schwarz
patent: 3040489 (1962-06-01), DaCosta
patent: 4259682 (1981-03-01), Gamo
patent: 4304043 (1981-12-01), Gamo et al.
patent: 4729971 (1988-03-01), Coleman

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